Skip to content
/ CPU-Classic-RISC-Pipeline-Machine Public

Made a fully functional CPU model capable of performing essential computing tasks, such as executing instructions from memory, handling data with load and store operations.

0 stars 0 forks Branches Tags Activity
Star
Notifications You must be signed in to change notification settings

jasonhsu93/CPU-Classic-RISC-Pipeline-Machine

BranchesTags

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

19 Commits
ALU.sv
ALU.sv
 
 
README.md
README.md
 
 
cpu.sv
cpu.sv
 
 
cpu_tb.sv
cpu_tb.sv
 
 
data.txt
data.txt
 
 
datapath.sv
datapath.sv
 
 
datapath_tb.sv
datapath_tb.sv
 
 
main.sv
main.sv
 
 
main_tb.sv
main_tb.sv
 
 
regfile.sv
regfile.sv
 
 
shifter.sv
shifter.sv
 
 

Repository files navigation

This project was part of a computer systems/architecture course, focused on enhancing a simple RISC (Reduced Instruction Set Computing) machine by integrating memory for storing instructions and data, and implementing memory-mapped I/O. The project required extending the datapath and finite-state machine controller and introducing advanced concepts like instruction memory and I/O interfacing.

image

Tech Stack: SystemVerilog, ModelSim Compiler, DE1-SoC (ARM7-based motherboard), Quartus Software

About

Made a fully functional CPU model capable of performing essential computing tasks, such as executing instructions from memory, handling data with load and store operations.

Topics

cpu armv7 datapath de1-soc risc

Resources

Readme
Activity

Stars

0 stars

Watchers

1 watching

Forks

0 forks
Report repository

Releases

No releases published

Packages

No packages published

Languages