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risc

Here are 55 public repositories matching this topic...

liuqdev / 8-bits-RISC-CPU-Verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

cpu fsm verilog risc

Updated Jan 20, 2019
Verilog

ustb-owl / Uranus

Uranus MIPS processor by MaxXing & USTB NSCSCC team

cpu fpga mips verilog risc

Updated Dec 14, 2019
Verilog

sudhamshu091 / Single-Cycle-Risc-Processor-32-bit-Verilog

Single Cycle RISC MIPS Processor

verilog risc risc-v risc-processor verilog-project

Updated Sep 17, 2021
Verilog

spider-tronix / VLSI

RISC V core implementation using Verilog.

cpu fpga processor computer-architecture risc verilog-hdl risc-v

Updated Mar 27, 2021
Verilog

darklife / udarkrisc

u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV

cpu fpga core processor rtl verilog risc softcore processor-design

Updated Jul 25, 2023
Verilog

djzenma / RV32IC-CPU

Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

cpu verilog risc hdl pipeline-processor verilog-hdl risc-v rv32i verilog-snippets pipeline-cpu risc-processor riscv32 riscv-simulator rv32imc verilog-code riscv32im

Updated May 29, 2020
Verilog

sudhamshu091 / Single-Cycle-Risc-Pipelined-Processor-Verilog

Single Cycle MIPS Pipelined Processor using Verilog

verilog risc risc-processor verilog-project pipelined-risc

Updated Aug 22, 2021
Verilog

qossayrida / PipelineProcessorDesign

Design and verification of a simple pipelined RISC processor in Verilog, featuring a five-stage pipeline and custom ISA.

verilog pipelining computer-architecture risc processor-design

Updated Jul 15, 2024
Verilog

simoneruffini / MELA

A Modestly Exhaustive dLx Architecture - RISC microprocessor - VHDL implementation - DLX ISA

vhdl microprocessor risc dlx p4adder t2logic t2shifter

Updated Apr 3, 2023
Verilog

arpit306 / 5-Stage-Pipelined-MIPS32-RISC-Processor-Design-on-Verilog

This repository contains the details and the code for the MIPS32 ISA based RISC Processor, which is implemented in 5 stage pipelined configuration.

verilog risc microprocessors nptel mips32

Updated Apr 26, 2023
Verilog

ibraheemalayan / Verilog_RISC_Processor

a simple multi-cycle RISC Verilog processor with architecture similar to MIPS

mips architecture university-project verilog computer-architecture risc

Updated Jul 12, 2023
Verilog

piotro888 / ppcpu

Pipelined PCPU

cpu core processor computer-architecture risc pcpu

Updated Nov 15, 2023
Verilog

ShwetaKiranTotla / Micro-processor-Design-Verification

Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.

python flash makefile verification uart risc testbench sdram sdram-controller cocotb cocotb-testing design-verification

Updated Oct 15, 2023
Verilog

Choaib-ELMADI / risc-v-on-de1-soc-fpga

A simplified RISC-V processor implemented in Verilog and deployed on the DE-1 SoC FPGA board.

programming fpga processor riscv verilog implementation de1-soc risc hdl fpga-soc risc-v fpga-board fpga-programming

Updated Apr 14, 2025
Verilog

digital-design-snu / ANPPV_RISC_PipelinedProcessor

pipeline processor architecture verilog vivado risc

Updated Apr 8, 2017
Verilog

KietLe11 / KLP32-RISCV

This project implements a simple RISC-V processor for FPGAs. It supports the RV32I base instruction set and is designed for educational and experimental purposes.

fpga risc risc-v rv32i riscv32 fpga-programming

Updated Apr 24, 2025
Verilog

yusronizza / riscv

RISC-V CPU Base Integer 32 bit ISA Implementation in Verilog HDL (Singlecycle, Multicycle, Pipelined). Update with more extension functionalities in the future.

open-source processor-architecture processor risc risc-v processor-design singlecycle-processor pipelined-processor

Updated Jan 7, 2025
Verilog

scarv / scarv-soc

SCARV: a side-channel hardened RISC-V platform

cryptography processor verilog risc soc risc-v xcrypto scarv

Updated Oct 29, 2021
Verilog

yumaueda / selevy

Simple implementation of RISC-V RV32IM CPU.

cpu verilog risc risc-v

Updated Aug 18, 2020
Verilog

ivanvig / MIPS

32-bit MIPS Implementation in Verilog

mips verilog computer-architecture risc microblaze

Updated Oct 8, 2020
Verilog

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