AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
-
Updated
Nov 21, 2025 - SystemVerilog
#
axi4-lite
Here are 10 public repositories matching this topic...
AXI4 and AXI4-Lite interface definitions
-
Updated
Sep 20, 2020 - SystemVerilog
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
systemverilog hardware-designs verilator axi4-lite axi4-protocol vivado-simulator axi4-lite-interface
-
Updated
May 4, 2024 - SystemVerilog
Formal AXI verification properties from the eXpect framework for secure SoC validation
verification eda systemverilog soc formal-verification axi amba hardware-security questa axi4 axi4-lite hardware-design
-
Updated
Oct 28, 2024 - SystemVerilog
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
vivado system-verilog verilator axi4 axi4-lite axi4-protocol axi4-lite-interface axi4-lite-system-verilog
-
Updated
May 4, 2024 - SystemVerilog
AXI4-Lite compatible Driver module for use with Verilator and other DPI-C compatible simulators.
-
Updated
Sep 15, 2022 - SystemVerilog
A UVM-based verification environment for a multi-core, write-back L2 cache on 32-bit RISC-V, enforcing MESI coherence with L1 caches and interfacing to DRAM over AXI4-Lite.
-
Updated
Nov 5, 2025 - SystemVerilog
This repo is based on the implementation of different peripherals and protocols like Axi4-lite , i2c and spi.
-
Updated
Sep 14, 2025 - SystemVerilog
Improve this page
Add a description, image, and links to the axi4-lite topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the axi4-lite topic, visit your repo's landing page and select "manage topics."