#
asic
Here are 71 public repositories matching this topic...
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds
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Sep 15, 2025 - Python
Allo: A Programming Model for Composable Accelerator Design
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Nov 7, 2025 - Python
A seamless python to Cadence Virtuoso Skill interface
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Feb 26, 2025 - Python
Cryptocurrency ASIC mining hardware monitor using a simple web interface
python asic monitor bitcoin mining cryptocurrency dash avalon hacktoberfest litecoin bitcoin-mining antminer bitmain antminer-monitor mining-monitor innosilicon
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May 1, 2023 - Python
ASIC implementation flow infrastructure
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Nov 8, 2025 - Python
Control and status register code generator toolchain
asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model
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Oct 10, 2025 - Python
A simplified and standardized interface for Bitcoin ASICs.
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Nov 3, 2025 - Python
Control and Status Register map generator for HDL projects
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May 24, 2025 - Python
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
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Nov 5, 2025 - Python
Generate UVM register model from compiled SystemRDL input
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Nov 5, 2025 - Python
Configurable AES-GCM IP (128, 192, 256 bits)
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Aug 27, 2025 - Python
A flexible and scalable development platform for modern FPGA projects.
asic fpga ci simulation test vhdl build-automation eda test-automation rtl verilog xilinx synthesis vivado systemverilog implementation vunit
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Oct 27, 2025 - Python
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