OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Index of the fully open source process design kits (PDKs) maintained by Google.

SKY130 ReRAM and examples (SkyWater Provided)

PLL x8 clock multiplier IP integrated onto the Efabless Caravel SoC

IHP 130nm ASIC tapeout of a 2x2 bfloat16 matrix matrix multiplication with DFT infrastructure. Iteration on the previous accelerator taped out on GF180.

Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process

Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process, embedded in efabless Caravel