VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
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Jan 4, 2022 - Verilog
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phase-locked-loop
Here are 8 public repositories matching this topic...
PLL x8 clock multiplier IP integrated onto the Efabless Caravel SoC
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Dec 8, 2020 - Verilog
All Digital Phase-Locked Loop (ADPLL)
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Jan 16, 2024 - Verilog
Extract the 15MHz clock signal from 400 picosecond pulse train
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May 4, 2023 - GLSL
Material from the course of Information Transmission at ENSEM - Université de Lorraine.
entropy huffman-coding telecommunications channel-coding qam-modulation bit-error-rate source-coding phase-locked-loop
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Sep 17, 2023 - MATLAB
Arduino library to communicate with Analog Devices ADF4110
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Mar 22, 2025 - C++
Variants of a Phase-Locked Loop (PLL) on a FPGA in the Labview programming environment
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Feb 10, 2025 - LabVIEW
This repository shows how to implement a simple PLL and a Frequency Meter using Arduino Uno.
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Aug 28, 2024 - HTML
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