Skip to content
GitHub Universe 2025
Explore 100+ talks, demos, and workshops at Universe 2025. Choose your favorites.
#

systolic-arrays

Here are 27 public repositories matching this topic...

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

  • Updated Jun 26, 2024
  • Verilog

This is my senior project. Aims to implement the AI accelerator self-test and self-recovery architecture proposed in the paper "STRAIT: Self-Test and Self-Recovery for AI Accelerator". STRAIT is a unified solution that provides self-test, self-diagnosis, and self-recovery functions for systolic array-based AI accelerators.

  • Updated Sep 2, 2025
  • Verilog

Improve this page

Add a description, image, and links to the systolic-arrays topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the systolic-arrays topic, visit your repo's landing page and select "manage topics."

Learn more