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Adds S-Mode to GC cores, allowing instantiation of msu_vp cores #22

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Merged
eyck merged 59 commits into from
Aug 27, 2025
Merged

Adds S-Mode to GC cores, allowing instantiation of msu_vp cores #22

eyck merged 59 commits into from
Aug 27, 2025

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@EAlexJ
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@EAlexJ EAlexJ commented Aug 1, 2025

This pull request does the following:

  • Adds msu_vp platform for RV32GC and RV64GC cores to factory
  • Corrects MMU to be architectural compliant for SV32 and SV39 (tested with RISC-V Architectural Compliance Test Suite)
  • small refactor of other privilege wrappers to increase readability
  • Adds missing CSRs to msu wrapper (those that are needed for address translation)

The new cores are only architectural compliant with the 'interp' backend, JIT backends might need quite extensive refactoring, see #21

eyck and others added 30 commits July 20, 2025 10:38
@eyck
fixes C++20 compatibility of SystemC wrapper
a13689b
@EAlexJ
removes shallow checkout for dbt-rise-core as refed commit cannot be …
0ce8463 
…found
@eyck
removes unused definitions
cd79f8c
@eyck
refactors arch state representation of generated cores
462257c
@eyck
fixes copy-paste error
cc21074
@EAlexJ
corrects commit tag of dbt-rise-core to allow building
b52822c
@eyck
adds msu privilege wrapper if ISA string contains 'gc'
59323c9
@eyck
remove left-over directories and fixes C++ Std level
56aa5b9
@eyck
fixes page-based access of memory_with_htif
40030b9
@EAlexJ
correcst typo
e8b7b63
@EAlexJ
corrects Usage for elfio test
9421422
@EAlexJ
adds more verbosity to unknown Instructions for interp
c7a48b8
@EAlexJ
fixes #19
c000fd6
@EAlexJ
removes medeleg and mideleg registers as spec states "In harts withou…
183d6e3 
…t S-mode, the medeleg and mideleg registers should not exist."
@EAlexJ
adds medeleg and mideleg to msu_vp
0c0676a
@EAlexJ
corrects medeleg behavior
ad6863a
@EAlexJ
removes magic numbers when setting trap state
49550d1
@EAlexJ
enforces C++ Standard Specification, makes clangd happy
858353a
@EAlexJ
corrects mmu, adds flushing mechanisms to priv wrapper
ebdc278
@EAlexJ
changes fence behavior for m and mu priv wrappers
12122c7
@EAlexJ
updates ISA submodule
d72d941
@EAlexJ
updates core.h, decouples regs from traits
ecfb414
@EAlexJ
updates interp cores, adds MSU privilege wrapper
19b825f
@EAlexJ
updates tgc5c.h to use fencevma instead of upper and lower
4a00b46
@EAlexJ
corrects interp template
c393063
@EAlexJ
adds corrected tgc5c interp
b1d72d1
@EAlexJ
corrects interp gc cores
012c8da
@EAlexJ
adds msu asmjit and llvm cores
f9a707d
@EAlexJ
checkin for mmu refactor
28879e7
@EAlexJ
changes msu wrapper to use the correct state for mstatus
1a17e6b
@EAlexJ EAlexJ requested a review from eyck August 1, 2025 12:53
EAlexJ and others added 19 commits August 2, 2025 13:21
@EAlexJ
removes error regarding duplicate case in msu wrapper
a67d0c5
@EAlexJ
improves mmu by moving check for page fault
5931742
@EAlexJ
changes Log Level for MMU
7f5162b
@EAlexJ
corrects typo for core registration
230e50b
@EAlexJ
corrects creation of arbitrary cores using the CLI
78cead4
@EAlexJ
allows loading of PIE Executables
c9adbd9
@EAlexJ
privilige wrappers now set S and U bit in misa
8b03fa2
@EAlexJ
adds scounteren reg to msu wrapper
3ab4343
@eyck
refactors sc_core_adapter interface to a facade
c4311f1
@eyck
fixes debug server interactions with cores
1c8e1be
@eyck
adds MISA modification based on privilege wrapper
82b7653
@EAlexJ
Revert "adds MISA modification based on privilege wrapper" as functio…
82f9996 
…nality is already implemented

This reverts commit 82b7653.
@EAlexJ
corrects mip writing in priv wrappers
f4bfd06
@eyck
fixes typo in gdb xml description of 64bit core
48f8983
@eyck
adds missing CSR names
0cd1755
@eyck
applies some cleanup on CSR registration
c99d195
@EAlexJ
removes single unused line in MMU
dda9a52
@EAlexJ
corrects rdcycle and rdcycleh behavior
7d410ea
@EAlexJ
addresses #23, adding handling of INSTRET and INSTRUCTION register, a…
8643187 
…lso correcting CYCLE Register
@eyck eyck merged commit 152e0cf into main Aug 27, 2025
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3 participants

@EAlexJ @eyck