Incorrect behavior when using CSR Instructions to access non-existent registers

[EAlexJ]

At the moment, CSR Instructions are not behaving as intended when accessing non-existent CSRs.
The issue is that after an unsuccessful / illegal read the instruction does not get aborted, rather it continues executing. In the case of CSRRW for example, this leads to writing the read value into rd.

This occurs as there are no checks after calling read_mem or write_mem to determine if they were successful.

[EAlexJ]

This error only exists for interp, as JIT backends already check the trap state after every memory access

[EAlexJ]

This error only exists for interp, as JIT backends already check the trap state after every memory access

Turns out this is not true, as the issue was not specific to the interp vm not taking return values into account but rather the privilege wrappers not even setting a trap state.