Adds S-Mode to GC cores, allowing instantiation of msu_vp cores

.envrc

@@ -1,3 +1,4 @@
+module load tools/vscode
 distro=`/bin/lsb_release -i -s`
 if [ $distro == "CentOS" ]; then 
     . /opt/rh/devtoolset-8/enable

CMakeLists.txt

@@ -12,15 +12,16 @@ include(GNUInstallDirs)
 include(flink)
 
 set(CMAKE_POSITION_INDEPENDENT_CODE ON)
+set(CMAKE_CXX_STANDARD_REQUIRED ON)
 
 include(FetchContent)
 if(NOT TARGET dbt-rise-core)
 	FetchContent_Declare(
 	    dbt_rise_core_git
 	    GIT_REPOSITORY  "https://github.com/Minres/DBT-RISE-Core.git"
 	    #GIT_TAG         "origin/develop"
-	    GIT_TAG         4d1bf6
-	    GIT_SHALLOW     ON
+	    GIT_TAG         718f877
+	    GIT_SHALLOW     OFF
 	    UPDATE_DISCONNECTED NOT ${UPDATE_EXTERNAL_PROJECT} # When enabled, this option causes the update step to be skipped.
 	)
 	FetchContent_GetProperties(dbt_rise_core_git)

CMakePresets.json

@@ -19,6 +19,7 @@
                 "CMAKE_INSTALL_PREFIX": "${sourceDir}/install/${presetName}",
                 "CMAKE_EXPORT_COMPILE_COMMANDS": "ON",
                 "CMAKE_PROJECT_TOP_LEVEL_INCLUDES": "contrib/cmake/conan_provider.cmake",
+                "CONAN_BUILD_PROFILE": "auto-cmake",
                 "WITH_TCC": "OFF"
             }
         },

gen_input/cores.core_desc

@@ -29,7 +29,7 @@ Core RV32IMAC provides RVI, Zicsr, Zifencei, RVM, RVA, Zca {
     }
 }
 
-Core RV32GC provides RVI, Zicsr, Zifencei, RVM, RVA, Zca, Zcf, Zcd {
+Core RV32GC provides RVI, Zicsr, Zifencei, RVM, RVA, Zca, Zcf, Zcd, RVSMode {
     architectural_state {
         XLEN=32;
         FLEN=64;
@@ -51,7 +51,7 @@ Core RV64I provides RVI, Zicsr, Zifencei {
     }
 }
 
-Core RV64GC provides RVI, Zicsr, Zifencei, RVM, RVA, Zca, Zcd {
+Core RV64GC provides RVI, Zicsr, Zifencei, RVM, RVA, Zca, Zcd, RVSMode {
     architectural_state {
         XLEN=64;
         FLEN=64;

gen_input/templates/CORENAME.h.gtl

@@ -43,21 +43,6 @@ def nativeSize(int size){
     if(size<=4096) return 4096;
     throw new IllegalArgumentException("Unsupported size in nativeSize in CORENAME.h.gtl");
 }
-def getRegisterSizes(){
-    def regs = registers.collect{nativeSize(it.size)}
-    regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
-    return regs
-}
-def getRegisterOffsets(){
-    def offset = 0
-    def offsets = []
-    getRegisterSizes().each { size ->
-        offsets<<offset
-        offset+=size/8
-    }
-    return offsets
-}
-
 def getCString(def val){
     return val.toString()+'ULL'
 }
@@ -73,62 +58,13 @@ def getCString(def val){
 namespace iss {
 namespace arch {
 
-struct ${coreDef.name.toLowerCase()};
-
-template <> struct traits<${coreDef.name.toLowerCase()}> {
-
-    constexpr static char const* const core_type = "${coreDef.name}";
-
-    static constexpr std::array<const char*, ${registers.size()}> reg_names{
-        {"${registers.collect{it.name.toLowerCase()}.join('", "')}"}};
-
-    static constexpr std::array<const char*, ${registers.size()}> reg_aliases{
-        {"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}};
-
-    enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
-
-    constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
-    constexpr static unsigned V_REGS_SIZE = ${constants.find {it.name=='VLEN'}?.value?:0};
-
-
-    enum reg_e {
-        ${registers.collect{it.name}.join(', ')}, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
-    };
+struct ${coreDef.name.toLowerCase()}: public arch_if {
 
     using reg_t = uint${addrDataWidth}_t;
 
-    using addr_t = uint${addrDataWidth}_t;
-
-    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
+    using virt_addr_t = iss::virt_addr_t;
 
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
-    static constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> reg_bit_widths{
-        {${getRegisterSizes().join(',')}}};
-
-    static constexpr std::array<const uint32_t, ${getRegisterOffsets().size()}> reg_byte_offsets{
-        {${getRegisterOffsets().join(',')}}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { ${spaces.collect{it.name}.join(', ')}, IMEM = MEM };
-
-    enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %>
-        ${instr.instruction.name} = ${index},<%}%>
-        MAX_OPCODE
-    };
-};
-
-struct ${coreDef.name.toLowerCase()}: public arch_if {
-
-    using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
-    using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
-    using reg_t =  typename traits<${coreDef.name.toLowerCase()}>::reg_t;
-    using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
+    using phys_addr_t = iss::phys_addr_t;
 
     ${coreDef.name.toLowerCase()}();
     ~${coreDef.name.toLowerCase()}();
@@ -200,6 +136,73 @@ if(vtype != null) {%>
 <%}%>
 };
 
+struct ${coreDef.name.toLowerCase()};
+
+template <> struct traits<${coreDef.name.toLowerCase()}> {
+
+    constexpr static char const* const core_type = "${coreDef.name}";
+
+    static constexpr std::array<const char*, ${registers.size()}> reg_names{
+        {"${registers.collect{it.name.toLowerCase()}.join('", "')}"}};
+
+    static constexpr std::array<const char*, ${registers.size()}> reg_aliases{
+        {"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}};
+
+    enum constants {
+        ${constants.collect{c -> c.name+"="+getCString(c.value)}.collate(4).collect { it.join(', ') }.join(',\n        ')}
+    };
+
+    constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
+    constexpr static unsigned V_REGS_SIZE = ${constants.find {it.name=='VLEN'}?.value?:0};
+
+
+    enum reg_e {
+        ${registers.collect{it.name}.join(', ')}, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
+    };
+
+    using reg_t = uint${addrDataWidth}_t;
+
+    using addr_t = uint${addrDataWidth}_t;
+
+    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
+
+    using virt_addr_t = iss::virt_addr_t;
+
+    using phys_addr_t = iss::phys_addr_t;
+
+    static constexpr std::array<const uint32_t, ${registers.size() + 7}> reg_bit_widths{{
+        ${registers.collect{'sizeof('+coreDef.name.toLowerCase()+'::'+coreDef.name+'_regs::'+it.name+') * 8'}.join(',\n        ')},
+        sizeof(${coreDef.name.toLowerCase()}::${coreDef.name}_regs::trap_state) * 8,
+        sizeof(${coreDef.name.toLowerCase()}::${coreDef.name}_regs::pending_trap) * 8,
+        sizeof(${coreDef.name.toLowerCase()}::${coreDef.name}_regs::icount) * 8,
+        sizeof(${coreDef.name.toLowerCase()}::${coreDef.name}_regs::cycle) * 8,
+        sizeof(${coreDef.name.toLowerCase()}::${coreDef.name}_regs::instret) * 8,
+        sizeof(${coreDef.name.toLowerCase()}::${coreDef.name}_regs::instruction) * 8,
+        sizeof(${coreDef.name.toLowerCase()}::${coreDef.name}_regs::last_branch) * 8,
+    }};
+
+    static constexpr std::array<const uint32_t, ${registers.size() + 7}> reg_byte_offsets{{
+        ${registers.collect{'offsetof('+coreDef.name.toLowerCase()+'::'+coreDef.name+'_regs, '+coreDef.name.toLowerCase()+'::'+coreDef.name+'_regs::'+it.name+')'}.join(',\n        ')},
+        offsetof(${coreDef.name.toLowerCase()}::${coreDef.name}_regs, ${coreDef.name.toLowerCase()}::${coreDef.name}_regs::trap_state),
+        offsetof(${coreDef.name.toLowerCase()}::${coreDef.name}_regs, ${coreDef.name.toLowerCase()}::${coreDef.name}_regs::pending_trap),
+        offsetof(${coreDef.name.toLowerCase()}::${coreDef.name}_regs, ${coreDef.name.toLowerCase()}::${coreDef.name}_regs::icount),
+        offsetof(${coreDef.name.toLowerCase()}::${coreDef.name}_regs, ${coreDef.name.toLowerCase()}::${coreDef.name}_regs::cycle),
+        offsetof(${coreDef.name.toLowerCase()}::${coreDef.name}_regs, ${coreDef.name.toLowerCase()}::${coreDef.name}_regs::instret),
+        offsetof(${coreDef.name.toLowerCase()}::${coreDef.name}_regs, ${coreDef.name.toLowerCase()}::${coreDef.name}_regs::instruction),
+        offsetof(${coreDef.name.toLowerCase()}::${coreDef.name}_regs, ${coreDef.name.toLowerCase()}::${coreDef.name}_regs::last_branch),
+    }};
+
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
+
+    enum sreg_flag_e { FLAGS };
+
+    enum mem_type_e { ${spaces.collect{it.name}.join(', ')}, IMEM = MEM };
+
+    enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %>
+        ${instr.instruction.name} = ${index},<%}%>
+        MAX_OPCODE
+    };
+};
 }
 }            
 #endif /* _${coreDef.name.toUpperCase()}_H_ */

gen_input/templates/asmjit/CORENAME.cpp.gtl

@@ -189,6 +189,7 @@ private:
         gen_set_tval(jh, instr);
         pc = pc+${instr.length/8};
         mov(cc, jh.next_pc, pc.val);
+        cc.mov(get_ptr_for(jh, traits::INSTRUCTION), instr);
 
         gen_instr_prologue(jh);
         /*generate behavior*/
@@ -276,13 +277,14 @@ template <typename ARCH>
 void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
     auto& cc = jh.cc;
 
-    cc.comment("//gen_instr_epilogue");
+    cc.comment("//Instruction epilogue begin");
+    cc.inc(get_ptr_for(jh, traits::CYCLE));
     x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
     mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
     cmp(cc, current_trap_state, 0);
     cc.jne(jh.trap_entry);
     cc.inc(get_ptr_for(jh, traits::ICOUNT));
-    cc.inc(get_ptr_for(jh, traits::CYCLE));
+    cc.inc(get_ptr_for(jh, traits::INSTRET));
     cc.comment("//Instruction epilogue end");
 
 }
@@ -360,10 +362,23 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
-volatile std::array<bool, 2> dummy = {
+<% if(instructions.find{it.instruction.name.toLowerCase() == "sret"}) {%>
+volatile std::array<bool, 3> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|msu_vp|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),<% } else { %>
+volatile std::array<bool, 2> dummy = {<%}%>
         core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
 		    auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -1096,7 +1096,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
             if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
             process_spawn_blocks();
             if(this->sync_exec && POST_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
-            pc.val = super::core.enter_trap(arch::traits<ARCH>::RV_CAUSE_FETCH_ACCESS<<16, pc.val, 0);
+            *PC = super::core.enter_trap(trap_state, pc.val, instr);
         } else {
             if (is_jump_to_self_enabled(cond) &&
                     (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
@@ -1128,8 +1128,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     break;
                 }// @suppress("No break at end of case")<%}%>
                 default: {
+                    if(this->disass_enabled){
+                        std::string mnemonic = "Illegal Instruction";
+                        this->core.disass_output(pc.val, mnemonic);
+                    }
                     *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
-                    raise(0,  2);
+                    raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                 }
                 }
             }catch(memory_access_exception& e){}
@@ -1169,10 +1173,23 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
-volatile std::array<bool, 2> dummy = {
+<% if(instructions.find{it.instruction.name.toLowerCase() == "sret"}) {%>
+volatile std::array<bool, 3> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|msu_vp|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),<% } else { %>
+volatile std::array<bool, 2> dummy = {<%}%>
         core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
 		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);

gen_input/templates/llvm/CORENAME.cpp.gtl

@@ -381,10 +381,23 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
-volatile std::array<bool, 2> dummy = {
+<% if(instructions.find{it.instruction.name.toLowerCase() == "sret"}) {%>
+volatile std::array<bool, 3> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|msu_vp|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),<% } else { %>
+volatile std::array<bool, 2> dummy = {<%}%>
         core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
 		    auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);

src/elfio.cpp

@@ -44,7 +44,7 @@ using namespace ELFIO;
 
 int main(int argc, char** argv) {
     if(argc != 2) {
-        printf("Usage: elfdump <file_name>\n");
+        printf("Usage: elfio-test <file_name>\n");
         return 1;
     }
 

src/iss/arch/mstatus.h

@@ -45,7 +45,11 @@ namespace arch {
 template <class T, class Enable = void> struct status {};
 // specialization 32bit
 template <typename T> struct status<T, typename std::enable_if<std::is_same<T, uint32_t>::value>::type> {
-    static inline unsigned SD(T v) { return bit_sub<63, 1>(v); }
+    static inline unsigned SD(T v) { return bit_sub<63, 1>(v); };
+    // Machine mode big endian
+    static inline unsigned MBE(T v) { return bit_sub<37, 1>(v); };
+    // Supervisor mode big endian
+    static inline unsigned SBE(T v) { return bit_sub<36, 1>(v); };
     // value of XLEN for S-mode
     static inline unsigned SXL(T v) { return bit_sub<34, 2>(v); };
     // value of XLEN for U-mode
@@ -90,6 +94,10 @@ template <typename T> struct status<T, typename std::enable_if<std::is_same<T, u
     // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR
     // XS==11)))
     static inline unsigned SD(T v) { return bit_sub<63, 1>(v); };
+    // Machine mode big endian
+    static inline unsigned MBE(T v) { return bit_sub<37, 1>(v); };
+    // Supervisor mode big endian
+    static inline unsigned SBE(T v) { return bit_sub<36, 1>(v); };
     // value of XLEN for S-mode
     static inline unsigned SXL(T v) { return bit_sub<34, 2>(v); };
     // value of XLEN for U-mode
@@ -185,6 +193,10 @@ template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T
     // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR
     // XS==11)))
     BF_FIELD(SD, 63, 1);
+    // Machine mode big endian
+    BF_FIELD(MBE, 37, 1);
+    // Supervisor mode big endian
+    BF_FIELD(SBE, 36, 1);
     // value of XLEN for S-mode
     BF_FIELD(SXL, 34, 2);
     // value of XLEN for U-mode