adds MISA modification based on privilege wrapper

Author: eyck

src/iss/arch/riscv_hart_msu_vp.h

@@ -188,6 +188,7 @@ template <typename BASE, features_e FEAT, typename LOGCAT>
 riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::riscv_hart_msu_vp()
 : mmu(base::get_priv_if())
 , default_mem(base::get_priv_if()) {
+    this->csr[misa] = traits<BASE>::MISA_VAL | (1 << ('U' - 'A')) | (1 << ('S' - 'A'));
     // common regs
     const std::array<unsigned, 16> rwaddrs{
         {mepc, mtvec, mscratch, mcause, mtval, sepc, stvec, sscratch, scause, stval, sscratch, uepc, utvec, uscratch, ucause, utval}};

src/iss/arch/riscv_hart_mu_p.h

@@ -183,6 +183,7 @@ template <typename BASE, features_e FEAT, typename LOGCAT>
 riscv_hart_mu_p<BASE, FEAT, LOGCAT>::riscv_hart_mu_p()
 : state()
 , default_mem(base::get_priv_if()) {
+    this->csr[misa] = traits<BASE>::MISA_VAL | (1 << ('U' - 'A'));
     const std::array<unsigned, 8> rwaddrs{{
         mepc,
         mtvec,

src/iss/debugger/riscv_target_adapter.h

@@ -378,7 +378,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std
         {"uint64", "longs", 64, 'l'},
         {"uint32", "words", 32, 'w'},
         {"uint16", "shorts", 16, 's'},
-        // { "ieee_half", 16, 'h', 'f' },
+        //{"ieee_half", "half", 16, 'h'},
         {"uint8", "bytes", 8, 'b'},
     }};