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Description
The current implementation does not correctly update the architectural state, namely the "supplemental" registers.
To prevent the JIT compiled code from doing unnecessary operations, the jit_holder holds values belonging to the architectural state (currently the pc and next_pc) and only writes them to the corresponding registers in case the JIT code gets exited by using write_back(jit_holder&). This happens for examples when plugins get called.
Issues arise as the JIT holder does not hold all values: some values just end up never being updated.
As done in DBT-RISE-RISCV, an implementation of the instrumentation_if might (sensibly) expect the architectural state to hold the correct values. Since plugins use the instrumentation interface to interact with the core (and thus directly the registers in the architectural state), this implementation is currently broken. Even further, as the instrumentation interface in general allows modifying the architectural state, these changes need to be reflected in the jit_holder upon returning back into the JIT code.
This issue is partly rooted here and partly in dbt-rise-core:
- dbt-rise-core needs to expand the jit_holder to cache all values that are not updated by the JIT code itself (such as the
instructionreg or other supplemental registers) - dbt-rise-core needs to update the cached values in the jit_holder when exiting any plugin in case the plugin changed the architectural state
- implementations of the vm_base need to update the values in the jit_holder. This means changing the templates to not only include the updates to the
jh.pcandjh.next_pc