vc-formal

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sashakatne / nvfp4-dotprod-formal-dv

Formal (VC Formal FPV) and UVM verification of an 8-lane mixed-precision INT8/BF16/NVFP4 dot-product core, with a shared SystemVerilog golden reference across assertions and scoreboards.

eda rtl systemverilog uvm formal-verification int8 sva dot-product questa hardware-verification mixed-precision design-verification bfloat16 nvfp4 vc-formal assume-guarantee

Updated Jul 4, 2026
SystemVerilog

sashakatne / FV_AHB2APB

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Formal verification (Synopsys VC Formal FPV/AEP) of a synchronous AMBA AHB-to-APB bridge — SVA assertions, bind files, bug-injection regressions, and a directed-simulation sanity check, with a formal-primary verification plan.

assertions rtl systemverilog formal-verification amba sva apb ahb design-verification vc-formal bus-bridge

Updated May 26, 2026
SystemVerilog

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