JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.

Simple UART transmitter and receiver

SUSTech 2024 Spring CS202 Course Project RISC-V 5-Stage-Pipeline CPU

Методичка по высшей цифровой схемотехнике + Verilog

UART controller that uses a master-slave architecture to enstablish a communication with the other device during the configuration process. This repository provides RTL code and testbench for the device synthesis and simulation, as well as a simple driver to use it in your system.

UART interface to a block ram in the Tang Nano 9k FPGA. No pin connections needed, just use the USB UART.

Alchitry Au FPGA Board Example Project

FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

Simple UART modules in SystemVerilog

A simple UART BFM

This is a re-write of my previous trigger project. This time Tang Nano 9k is the target hardware and the USB UART is used to configure and enable triggering.

Tea Encryption for ECE 4304 VHDL Design Project

UART interface to a block ram in the Tang Nano FPGA. No pin connections needed, just use the USB UART.

UART Tx implemented in SystemVerilog from scratch.

UART Peripheral written in SystemVerilog

A compact SystemVerilog SoC implementing a RV32IM CPU with memory‑mapped GPIO, UART and Timer peripherals on a Wishbone bus. Instruction memory is JTAG‑programmable and the repo includes Verilator testbenches plus a gcc-based toolchain to build C programs and generate Verilog‑readable instruction images.

UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.

RISC-V SoC

This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.