Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
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Mar 28, 2026 - Python
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systemrdl
Here are 13 public repositories matching this topic...
Simulation and implementation flow for hardware description languages
asic fpga simulation vhdl verilog vivado systemverilog implementation questasim quartus systemrdl cocotb synopsys-vcs
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Sep 17, 2026 - Python
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
asic fpga verilog rdl systemverilog hdl registers systemrdl systemrdl-compiler hardware-description-language register-description-language
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Nov 27, 2021 - Python
Semantic compatibility analysis and configurable quality gates for SystemRDL specifications. Detects firmware-breaking register changes, produces CI reports and provides scalable exploration of large register maps.
asic fpga eda csr registers systemrdl register-descriptions systemrdl-compiler hardware-description-language design-automation register-description-language
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Jul 17, 2026 - Python
Tapeout Object Format (.tapeout) - flat-text hardware integration contract (parser + emitter)
python serialization parser hardware verification eda rtl ip systemverilog soc systemrdl tapeout chip-design register-map
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Aug 14, 2026 - Python
SystemRDL lexer for Pygments syntax highlighting
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Jun 19, 2025 - Python
Open-source, local-first SoC collateral consistency checker for RTL, Liberty, LEF/DEF, IP-XACT, SystemRDL, SDC, UPF, connectivity CSV, package maps, CDL/GDS, and C headers.
asic static-analysis eda rtl verilog connectivity liberty ip-xact systemverilog sdc soc cdl upf systemrdl def electronic-design-automation hardware-verification lef consistency-checker register-map
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Oct 12, 2026 - Python
A layered pyuvm verification environment on a 16550-style APB UART, from RTL to GDS. Built from the ChipForAll template.
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Oct 11, 2026 - Python
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