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systemrdl

Here are 2 public repositories matching this topic...

hughjackson / PeakRDL-verilog

Generate verilog register file from systemRDL description

asic fpga rtl verilog systemrdl

Updated Feb 9, 2024
SystemVerilog

cirofabianbermudez / pyralgen

A lightweight Python-based code generator to produce RAL UVM with coverage

asic fpga systemverilog uvm systemrdl

Updated Jul 8, 2025
SystemVerilog

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