Control and Status Register map generator for HDL projects
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May 24, 2025 - Python
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system-verilog
Here are 13 public repositories matching this topic...
openENOC is an open-source Ethernet-based NoC for scalable MPSoC systems, using Layer-2 frame switching to connect CPUs, accelerators and peripherals for crypto, AI and edge computing.
acceleration networking fpga riscv rtl ethernet soc system-verilog risc-v mpsoc noc network-on-chip gateware
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Jul 25, 2026 - Python
Example of Python and PyTest powered workflow for a HDL simulation
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Jan 17, 2021 - Python
Spice to Verilog Converter
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May 23, 2023 - Python
Templates generator: make Verilog/SystemVerilog module template by parameters and ports list
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Jan 2, 2023 - Python
Build tools for dau projects
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Aug 4, 2026 - Python
Cycle-accurate hardware simulator
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Aug 4, 2026 - Python
HBM4 System Modeling Platform - High Bandwidth Memory simulation and verification framework
python dram uvm system-verilog hbm semiconductor memory-controller chip-design high-bandwidth-memory hbm4
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Jul 8, 2026 - Python
Segundo proyecto para el curso de Arquitectura de Computadores. La idea es hacer un ASIP (Application Specific Set Processor) que genere interpolación de imagen por medio de un compilador, código en ensamblador, un procesador pipeline y scripts en alto nivel.
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May 19, 2022 - Python
A Graph Neural Network framework for detecting hardware Trojans in gate-level .v and .sv netlists; RTL inputs are synthesized via Yosys before classification. Six-stage pipeline (ingestion → parsing → synthesis → graph construction → GNN classification with GCN/GAT/GIN → reporting), with cascade and ensemble inference and per-gate localization.
deep-learning pytorch verilog system-verilog hardware-security electronic-design-automation graph-neural-networks pytorch-geometric hardware-trojans
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May 22, 2026 - Python
This repository aims to automatically generates source files for HDL
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Jun 5, 2019 - Python
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