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system-verilog

Here are 60 public repositories matching this topic...

HaDes-V

tscheipel / HaDes-V

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design

Updated Jun 5, 2025
SystemVerilog

Weiyet / RTLStructLib

RTL data structure

data-structures rtl system-verilog verilog-hdl cocotb uvm-verification

Updated Aug 10, 2025
SystemVerilog

pulp-platform / trace_debugger

Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.

system-verilog risc-v debugging-tool instruction-trace

Updated Mar 13, 2024
SystemVerilog

kinap / AES-Processor

AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.

cryptography fpga aes emulation system-verilog veloce

Updated Mar 22, 2017
SystemVerilog

Amirarsalan-sn / RISCV-multi-cycle-processor

A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL

cpu hardware risc hdl modelsim system-verilog risc-v quartus multi-cycle-processor

Updated Jun 5, 2023
SystemVerilog

flasonil / Serial-Multiplier

16 bit serial multiplier in SystemVerilog

verilog systemverilog system-verilog verilog-project

Updated Oct 13, 2018
SystemVerilog

rubinsteina13 / SV_I2S_RX_CORE

Synthesizable SystemVerilog IP-Core of the I2S Receiver

fpga verilog systemverilog hdl system-verilog cpld i2s i2s-dac ip-core asic-design

Updated Jun 7, 2020
SystemVerilog

flasonil / APB_PWM

Pulse Width Modulator programmed through an Advanced Peripheral Bus interface

verilog system-verilog

Updated May 15, 2018
SystemVerilog

kumarrishav14 / ALU_UVM

UVM Test bench for a 8-bit ALU

alu uvm system-verilog design-verification

Updated Dec 24, 2020
SystemVerilog

Awais-Asghar / Single-Cycle-RISC-V-Processor-Implemented-on-FPGA

An FPGA-based single-cycle RISC-V processor (RV32I) implemented in SystemVerilog. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. This project is ideal for learning computer architecture, digital design, and RISC-V ISA implementation.

fpga vivado computer-architecture system-verilog risc-v cpu-architecture processor-design single-cycle-processor digital-design-and-computer-organization rv32i-processor

Updated Jul 21, 2025
SystemVerilog

EliasManj / Verilog-PS2-LCD-Interface

Quartus II project for a basic interface for writing in a LCD screen using a PS2 keyboard using Altera DE2-70 board

finite-state-machine lcd-display system-verilog ps2-keyboard

Updated Oct 30, 2017
SystemVerilog

mrLSD / riscv-cpu

RISC-V five stage pipline CPU

cpu system-verilog risc-v risc-processor pipline

Updated Jul 26, 2019
SystemVerilog

gvilardefarias / Hardware-Data-Structures

A systemverilog implementation of the data structures: priority queue, queue and stack

system stack hardware open-hardware priority-queue data-structures rtl verilog systemverilog fifo hdl system-verilog hardware-description-language

Updated Apr 2, 2020
SystemVerilog

imjp2020 / UVM_FIFO_TB

This testbench is based on SV and UVM Class based to verify Verilog HDL Design

uvm system-verilog verilog-hdl

Updated Mar 23, 2023
SystemVerilog

muhammadtalhasami / Axi4_lite_interface

This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .

vivado system-verilog verilator axi4 axi4-lite axi4-protocol axi4-lite-interface axi4-lite-system-verilog

Updated May 4, 2024
SystemVerilog

shyamal-anadkat / The-11-of-us

quadcopter vhdl flight-controller verilog synthesis adc uart hdl system-verilog integrator ece551

Updated Dec 11, 2017
SystemVerilog

abdullah8a0 / one-chan

An FPGA-based Chess Engine and TPU

chess-engine fpga system-verilog tpu

Updated Feb 9, 2023
SystemVerilog

ayusdixit / Digital-ASIC-LAB

Verilog Codes for various Design

pipeline multiplication verilog fifo uvm adder system-verilog verilog-hdl max-pooling sequence-detector one-detector reconfigurable-matrix-adder

Updated Nov 24, 2023
SystemVerilog

helcsnewsxd / armv8-pipelined-hazard-handling

Pipelined ARMv8 with hazard detection and forwarding - Computer Architecture course project - Computer Science @ FAMAF (UNC)

python processor-architecture analysis assembly lab university-project forwarding computer-architecture hazard-detection system-verilog armv8 quartus hardware-description-language processor-design famaf pipelined-processor

Updated May 27, 2025
SystemVerilog

JoseDavidSS / TDD.Single-Cycle_Processor

Proyecto Final para el curso de Taller de Diseño Digital. La idea es hacer un procesador uniciclo para procesar un texto utilizando los lenguajes de programación ARM, Python y SystemVerilog.

python arm processor intel armv7 system-verilog digital-design quartus-prime unicycle

Updated May 5, 2022
SystemVerilog

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