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SystemRDL / PeakRDL

Control and status register code generator toolchain

asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model

Updated Sep 1, 2026
Python

Claude Code / Codex CLI skill that scaffolds a runnable UVM testbench (APB / AHB-Lite / AXI4-Lite + generic-bus fallback) from an IP spec and register table, with a UVM-sequence flow for DV and a tb_api:: task BFM for DE.

Updated Jul 14, 2026
Python

tonythetiger168 / open-vip-portfolio

Star

132 protocol entries: 110 UVM VIPs + 22 RTL IP companions (AMBA/DDR/PCIe/CXL/USB/MIPI...) — L1-L4 SVA, smoke-verified, pyslang/iverilog/verilator gates. Apache-2.0.

coverage asic fpga verification vip riscv systemverilog uvm formal-verification testbench pcie amba memory-controller hardware-verification chip-design

Updated Oct 3, 2026
Python

SandeepGorrepati / apb-regfile-cocotb

Star

AMBA APB4 register-file slave verified with cocotb: BFM, reference-model scoreboard, functional coverage, PSLVERR error paths. 300 constrained-random transactions, 0 mismatches, 100% coverage; CI.

python verification verilog systemverilog vlsi amba apb cocotb functional-coverage

Updated Jun 26, 2026
Python

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