Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )

"Mastering RTL-Coding : From Fundamentals to Advanced Programming Techniques using Verilog,System Verilog and UVM"

An implementation of AMBA AXI4Lite on an FPGA using verilog

AHB2APB Bridge Converter (Implementing one of the AMBA protocol)

AMBA AHB-lite studyroom

This project implements and verifies the Advanced Peripheral Bus (APB) Protocol, a part of the AMBA (Advanced Microcontroller Bus Architecture) developed by ARM. The APB is designed for low-power, simple peripheral communication in System-on-Chip (SoC) designs.

Single Master Multiple Slave AHB protocol is carried out. Necessary images of architecture used are also attached. Pls check them out!

A comprehensive clock management IP core with multiple divider types and glitch-free switching

This repository contains the source code and results for AMBA AHB to APB Bridge design performing single read, single write and burst write transfers. The design is coded in Verilog, using Modelsim simulator and synthesized using Quartus Prime software.

This repo will contain the Verilog code implementation of various protocols that fall within AMBA protocol family such as APB, AHB, AXI and so on. I will implement it in parallel with learning theory. If possible I will also use UVM and system verilog to verify the functionality of the code once I finish learning system verilog and concepts of uvm