Advanced peripheral bus is part of AMBA protocol family and is a simple non-pipelined protocol which supports low-bandwidth transactions.
It has 3 operating states - IDLE, SETUP and ACCESS.
The state diagram is shown below -
The interconnections between APB master and slave are as shown below -
The waveform for writing without wait state looks like this -
In the above image, T0-T1 is IDLE phase, T1-T2 is SETUP phase and T2-T3 is ACCESS phase.
The verilog code for the same is written above.
-
Notifications
You must be signed in to change notification settings - Fork 0
This repo will contain the Verilog code implementation of various protocols that fall within AMBA protocol family such as APB, AHB, AXI and so on. I will implement it in parallel with learning theory. If possible I will also use UVM and system verilog to verify the functionality of the code once I finish learning system verilog and concepts of uvm
ubyhzargam/AMBA-Protocol-Family
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
This repo will contain the Verilog code implementation of various protocols that fall within AMBA protocol family such as APB, AHB, AXI and so on. I will implement it in parallel with learning theory. If possible I will also use UVM and system verilog to verify the functionality of the code once I finish learning system verilog and concepts of uvm
Topics
Resources
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published