Machine learning on FPGAs using HLS

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".

[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.

FPGA implementation of Canny edge detection by using Vivado HLS

FPGA acceleration of arbitrary precision floating point computations.

This project implements a convolution kernel based on vivado HLS on zcu104

MNIST accelerator using binary qunatization on Xilinx pynq-z2

Source codes for High Level Synthesis for Fixed Progammable Gate Arrays (FPGAs). Can be converted to RTL using Vivado HLS or SDSoC.

CPU implementation of the Image stitching using FAST. For FPGA implementation visit tharaka27-SocStitcher.

FPGA Cryptography for High-Level Synthesis

Implementation of the N^2-formulation of N-body simulation with Vivado HLS for SDAccel platforms.

Implementation of time and space-tiled stencil in Vivado HLS.

QPSK system implemented using Vivado HLS

Vitis (Vivado) HLS Examples

Accelerated Stencil Computation with Optimized Dataflow Architecture on FPGAs

Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)

This implementation of RSA is on an FPGA platform to test the performance of the algorithm in terms of latency as a comparison to AES

Designing local adaptive thresholding using integral images from scratch. "Efficient Implementation of Local Adaptive Thresholding Techniques Using Integral Images" by Faisal Shafait, Daniel Keysers, Thomas M. Breuel was used as guideline.