FPGA Accelerator for CNN using Vivado HLS
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Oct 25, 2021 - C++
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sdsoc
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IIoT-SPYN gives users the ability to control, monitor, capture data, visualize and analyze industrial grade motors
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Mar 19, 2020 - Tcl
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Feb 26, 2020 - C++
Source codes for High Level Synthesis for Fixed Progammable Gate Arrays (FPGAs). Can be converted to RTL using Vivado HLS or SDSoC.
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Apr 5, 2019 - C++
Visual System Integrator - Accelerate your embedded development
embedded
fpga
zynq
integration
hls
accelerator
cnn
rapid
accelerate
lenet
xilinx
vivado
sdx
rapid-development
mpsoc
fpga-accelerator
high-level-synthesis
sdsoc
virtex7
xilinx-zynq
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Jun 18, 2018 - Python
xfOpenCV Optical Flow implemented on Zedboard with built aarch32 OpenCV libraries
opencv
arm
revision
webcam
optical-flow
cross-compile
zedboard
petalinux
webcam-capture
aarch32
sdsoc
webcamera
xfopencv
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Jan 16, 2020 - C++
deep-neural-networks
ai
fpga
deep-learning
dnn
artificial-intelligence
mnist
artificial-neural-networks
ann
sdsoc
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Dec 15, 2017 - Objective-C
Projects for snickerdoodle black
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Jun 9, 2024 - HTML
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