Implementation of DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications in verilog
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May 5, 2021 - Python
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verilog-project
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Deep Learning based Finite State Machine implementation of a Smart Lock System
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Dec 8, 2020 - Python
Traffic light controller for three way intersections
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Nov 25, 2024 - Python
A complete setup for Qflow, an open-source digital VLSI design flow. This repo provides pre-configured example projects, automated installation scripts, and step-by-step instructions to synthesize, place, and route Verilog designs into GDSII layouts. Supports both running example designs and using your own Verilog.
yosys verilog-project qflow graywolf digital-vlsi gdsii-flow magic-vlsi netgen-layouts vlsi-automation
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Sep 7, 2025 - Python
Provide a basic structure to starts a Verilog or Systemverilog project. Create a Verilog Design Flow based on Makefiles, Iverilog, GTKwave. Create a VS Code environment with Linting (verilator and verible), formatting and Language Server (verible)
language-server linting formatting vscode test-automation verilog systemverilog gtkwave verilog-hdl iverilog verilator verilog-project vscode-environment verible linting-workflow
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Nov 18, 2025 - Python
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