A digital safe designed in Vivado, which has a 4 digit decimal password, and is implemented on PYNQ-Z2 board and RPI-Logic board
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Updated
Jul 1, 2024 - Tcl
A digital safe designed in Vivado, which has a 4 digit decimal password, and is implemented on PYNQ-Z2 board and RPI-Logic board
Implementação de um relógio digital usando descrição de hardware e prototipado numa FPGA.
This is a 4*4 Array_Multiplier_project using Verilog HDL. This is successfully implemented on FPGA board.
RISC-V single-cycle processor written in Verilog using the Quartus tool. Implementation of bubble sort through assembly language.
The objective is to design basic sequential circuits in Verilog and implementing them on an FPGA.
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