verilog-project

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pescetti-studio / FliPGA01

FPGA (Verilog) implementation of the Flip01 8-bit processor.

cpu fpga verilog 8bit 8-bit verilog-project 8-bit-cpu 8-bit-computer flip01

Updated Dec 30, 2024
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SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

hardware systemverilog hardware-designs sdram sdram-controller verilog-project

Updated Jul 1, 2022
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djzenma / 2-FPGAs-UART-Protocol

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Transmitter and Receiver FPGAs connected using the UART Protocol to execute arithmetic operations and display the inputs on the transmitter's 7 Segment Display as well as the result on the Receiver's 7 Segments Display.

fpga verilog hardware-designs uart-protocol verilog-project