Verilog for ASIC Design
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Sep 13, 2021 - Verilog
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testbench
Here are 54 public repositories matching this topic...
Trying to get a new skill
digital electronics rtl verilog xilinx vivado altera modelsim testbench xilinx-vivado quartus-prime gowin
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Dec 31, 2024 - Verilog
Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
spi-interface rtl verilog spi hdl testbench verilog-hdl wishbone spi-master spi-protocol spi-slave verilog-project clock-generator verilog-code verilog-rtl-model wishbone-master
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Jul 7, 2024 - Verilog
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
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Aug 4, 2024 - Verilog
5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.
arm pipeline cache processor verilog systemverilog computer-architecture testbench verilog-hdl risc-v digitaldesign axi3
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Dec 21, 2024 - Verilog
probable journey of RTL coding ft. Chandra Prakash
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Mar 14, 2024 - Verilog
Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.
python flash makefile verification uart risc testbench sdram sdram-controller cocotb cocotb-testing design-verification
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Oct 15, 2023 - Verilog
The project description of this project was the major project in the Computer Architecture course. It's a RISC-V processor and tested on Nexys A7 kit.
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Feb 9, 2021 - Verilog
16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.
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May 14, 2021 - Verilog
An easy approach for Conway's Game Of Life with Verilog HDL
game-of-life verilog testbench verilog-hdl conways-game-of-life game-of-life-verilog verilog-game-of-life conways-game-of-life-verilog
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Sep 21, 2023 - Verilog
Built-In-Self-Test blocks using LFSRs and MISRs for a circuit under test made in Verilog
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Apr 6, 2025 - Verilog
This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.
fpga ram hardware verilog synchronous testbench digital-circuits hardware-description-language single-port fpga-programming memory-design
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Aug 24, 2024 - Verilog
Basic scan chain block implemented in Verilog
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Apr 6, 2025 - Verilog
Basic JTAG standard implementation in Verilog and integration with a CUT
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May 9, 2025 - Verilog
This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.
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May 16, 2024 - Verilog
This repository is about the main project of the course "VLSI System Design". This course is part of my undergraduate studies on University of Thessally - ECE Department located in Volos, Greece.
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Nov 25, 2024 - Verilog
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