RISC-V microcontroller IP core developed in Verilog

Basic RISC-V Test SoC

The Antikernel operating system project

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

Fireboy & Water Girl in the Forest Temple implemented on an FPGA board for UIUC's ECE385 Digital Systems Laboratory.

A ZipCPU SoC for the Nexys Video board supporting video functionality

Senior Design

A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier

Mixed-Signal Oscilloscope on Chip

Trying to implement a soft core SoC

Documented my learnings of the System-on-Chip course using Verilog. Verilog enthusiasts interested in adding more VHDL concepts into this repository are more than welcome to fork, clone and add contributions!

A study of soft-core CPUs for use with FPGA designs

The goal of ECE 385 course is to teach students to design, build, and test/debug a digital system, which can be a 16-bit microprocessor, a dedicated logic core, or a system-on-a-chip (SoC) platform

FPGA Implementation of a Security Module as Open Source

5-stage pipelined MIPS CPU with memory-mapped I/O, GPIO, and factorial accelerator on FPGA

This project showcases a Verilog implementation of an System on Chip design where the RISC-V processor is connected to multiple peripherals using APB bus

An FPGA-based RISC-V SoC to mess around with

This repository is about the main project of the course "VLSI System Design". This course is part of my undergraduate studies on University of Thessally - ECE Department located in Volos, Greece.