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system-on-chip
Here are 6 public repositories matching this topic...
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds
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Mar 25, 2026 - Python
System on Chip toolkit for Amaranth HDL
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May 23, 2026 - Python
System-on-Chip Resource Adaptive Scheduling using Deep Reinforcement Learning
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Nov 2, 2022 - Python
Examples of using Litex on an Alchitry Cu board
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Feb 4, 2024 - Python
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