This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II

This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from sys…

RTL to GDSII flow of a low Power configurable multi clock digital system

Complete design of USART interface with baud rate selection

RV32E201X is a 5-stage pipelined 32-bit RISC-V processor core.

Design and Implementation of Goertzel Algorithm for DTMF application on ASIC.

My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools

4-bit serial multiplier implementation in Verilog HDL with Moore FSM control. Features serial I/O conversion, comprehensive synthesis analysis, and complete design documentation including timing analysis and place-and-route results.

This repository contains the final project of my Physical Design Internship at ICpedia. The goal was to implement a complete RTL-to-GDSII flow for the wbqspiflash design using the OpenROAD & OpenLane toolchain