Pinned Loading

1. ASIC_implementation_of_PULPino_SoC ASIC_implementation_of_PULPino_SoC Public

   My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools

   Verilog 2

2. DSP_Custom_AXI_IPs DSP_Custom_AXI_IPs Public

   Work under progress.

   SystemVerilog 2

3. My_Verification_work My_Verification_work Public

   A repo for my System Verilog testbenches with test benches for UART, I2C, SPI, FIFOs and Bus protocols like AMBA, AHB and WISHBONE

   SystemVerilog 3 1

4. ASICs_Design_Diploma ASICs_Design_Diploma Public

   RTL to GDSII flow of a low Power configurable multi clock digital system

   Verilog 2 1

5. 4_Channel_Logic_Analyzer 4_Channel_Logic_Analyzer Public

   FPGA based Logic analyzer designed then FPGA implemented on ALTERA cyclone IV FPGA

   Verilog 3

6. ASU-ICL-Low-Cost-Brucella-Sensing-Solution ASU-ICL-Low-Cost-Brucella-Sensing-Solution Public

   EIS based solution for sensing Brucella in milk based on ESP32 low cost MCU with MATLAB in the loop affiliated with Ain Shams University IC lab supervised by professor Hani Fikry

   MATLAB