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openroad
Here are 13 public repositories matching this topic...
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds
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Sep 15, 2025 - Python
Photonic Integrated ELectronics. Microservices to codesign photonics, electronics, quantum, and more.
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Jul 1, 2025 - Python
Physical Design of Mixed signal circuit that performs- "In Memory logic using 8TSRAM cells" using OPENFASOC.
magic sram ngspice align in-memory-computations openroad mixed-signal-chips physicaldesign openfasoc
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Jul 11, 2023 - Python
Model Context Protocol (MCP) server for OpenROAD
python mcp eda vlsi physical-design openroad asic-design ai-tools chip-design model-context-protocol fastmcp
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Jan 18, 2026 - Python
TinyTapeout GDS blackbox macro testing
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Sep 9, 2024 - Python
Given an OPENRoad subcircuit file, this program will use SPICE to simulate worst-case speed-up and slow-down due to the Multiple-Input-Switching effect. Designed for CSE 222B Advanced VLSI SQ25 with Mitchell Tansey.
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Jul 30, 2025 - Python
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