A High-performance Timing Analysis Tool for VLSI Systems
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
5 Day TCL begginer to advanced training workshop by VSD
TCL Script automating the frontend of ASIC design
This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.
UPSET is an automated framework for performing Single Event Transient Analysis and Optimisation for VLSI circuits utilising Static Timing Analysis principles. Documentation at:
A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)
An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.
Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - Verilog HDL Projects
CAD in NYCU
Open-source EDA × AI for chip design. Graph-native, local-first tools for STA, GPU-parallelism, and hardware security.
Microprocessor Design using Verilog HDL built and tested in Vivado Design Suite
High-performance, in-RAM HDL processor, Cranelift JIT simulator, and physics-informed silicon telemetry engine in Rust.
A Roadmap application for ECE students from NIT college student based knowledge
Static timing analysis with signal integrity — WNS/TNS sign-off gate, SI/crosstalk + statistical OCV.
An interactive git diff for VLSI timing signoff; visually compares two STA reports before and after a design change, instantly showing which paths sped up, slowed down, or newly violated timing.
Verified LeNet-5 int8 inference datapath in SystemVerilog, with a bit-exact Python oracle and real sky130hd PPA (pre-layout).
Signed-off 8-bit RISC-V-style ALU from SystemVerilog RTL to GDSII using OpenLane 2.3.10 and SKY130A.
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