MIPS implementation

Optical sensor to detect hazardous gas in corrosive environment. Showcasing my Raspberry Pi project combining electrical engineering and sensor detection.

ahead of the weather curve

5-stage pipelined 32-bit MIPS processor

The research mainly aims to identify through classification algorithms if one day, based on its climatic features and concentrations of harmful elements in the air, it turns out to be harmful (or not) to the health of citizens in the Milan metropolis. A second prediction model was adopted to predict daily mean PM2.5 values.

The Hazard Recognition Challenge allows you to perform a virtual workplace examination. Your goal is to find as many hazards as possible at a work location.

Structure of Computer Systems course (3rd year, 1st semester)

Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor

Architecure for the Data path and Controller as well as Hazard Units for a 32 bit ARM based Single Cycle, Multi Cycle and Pipelined Based Processor

The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.

Computer organisation and architecture assignments

A 32-bit Arm Processor Using Verilog HDL With Hazard Detection, Forwarding Unit, SRAM Memory & A 2-Way Set-Associative Cache.

A paper exploring emotional contagion within the context of crowd simulation.

Verilog Implementation of an ARM LEGv8 CPU

CURSO - Taller de Sistemas de Información Geográfica aplicados a Desarrollo y Ordenamiento Territorial (OT) - SIGE

Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.

Smart Building Evacuation Ontology

Python GUI-based hazard video labelling