Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).

A compiler, assembler, and processor.

A neural branch predictor tested using CPU emulator, testing both supervised learning and reinforcement learning (for COS 583: Great Moments in Computing at Princeton University)

同济大学CS《计算机系统实验》实验一TongJi University CS computer system experiment assignment 1

Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4

VHDL code of three branch predictors

Branch Predictor is a C# program that runs a gshare branch prediction simulation, according to a specified number of Global Buffer Table (GBT) and Global History Record (GHR) bits. 2019.

MIPT-V Pipeline Flowchart Visualizer

Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.

Branch prediction using branch correlations. Made as part of the course Data-driven Program Analysis (CS686)

Project done as a course-project for CS422 (Computer Architecture) at IIT Kanpur, in April-March 2015, under guidance of prof. Mainak Chaudhuri. Idea is to implement the popular perceptron based branch predictors for different memory limits and evaluate the performance on CBP-2014 kit. Also try to explain the performance result.

Simulation of a bimodal two-level single branch/jump predictor, implemented in Python, for High Performance Processors (2022-23).

C++ Macro definitions for easy branch hinting.

Labs in NYU Tandon 2019 Fall CSA course

Processor RISC-V and application

Computer Architecture

Educational project aimed at evaluating the effectiveness of different correlating branch predictors on benchmarks