CPEN 211: Introduction to Microcomputers 2022W1 with Prof. Lis

bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications

ALU Built with proper Datapath and Control path (FSM) to give appropriate results

University project about the game rock-paper-scissors

𝗠𝗶𝗻𝗶𝗠𝗜𝗣𝗦 | 𝗥𝗜𝗦𝗖 𝗣𝗿𝗼𝗰𝗲𝘀𝘀𝗼𝗿 𝗗𝗲𝘀𝗶𝗴𝗻 | CS39001 𝗖𝗼𝘂𝗿𝘀𝗲 𝗣𝗿𝗼𝗷𝗲𝗰𝘁

This was the project assignment for the Digital Logic Design course.

Uni project about the game rock-paper-scissors

Architecure for the Data path and Controller as well as Hazard Units for a 32 bit ARM based Single Cycle, Multi Cycle and Pipelined Based Processor

Single Cycle MIPS Datapath implementation in Verilog that extends the standard MIPS architecture with seven custom instructions, featuring a complete processor design with control unit, ALU, register file, and memory components.

Learned as a part of Computer architecture Course

Datapath and Control for a Turing Complete ISA with Interrupt Handling

Greatest Common Divisor calculator showcasing CPU-like controller + datapath architecture using subtraction-based Euclidean algorithm. Demonstrates synthesizable FSM design vs behavioral modeling trade-offs with complete hardware implementation.

Repositório para o trabalho final da disciplina de Circuitos e Técnicas Digitais do Prof. Héctor Pettenghi Roldán.

Implementação do Projeto Final da Disciplina de Sistemas Digitais, oferecia pelo Departamento de Engenharia Elétrica da UFMG. O Projeto elabora um sistema de cofre digital, seguindo a metodologia de Resgister Transfer Level.