微电子和集成电路自学指南

Converting Boolean expressions to CMOS Circuits

This repository contains a CMOS inverter circuit designed and simulated using LTspice. A CMOS inverter which is actually a "Hello World" in VLSI design logic is a fundamental building block in digital electronics, and this project aims to showcase its operation and characteristics.

A project for designing and implementing TTL to CMOS and CMOS to TTL interfacing in a microcontroller environment using NGSPICE. The code includes simulations and analysis of signal behaviour across different logic families.

Design and Layout implementation of a high-performance two-stage Operational Amplifier (OPAMP) using180nm semiconductor technology. Achieved required gain, bandwidth, and power efficiency through simulation and characterization.

This repository contains some the codes to simulate various operations and characteristics of MOS circuits

Designing JK Flip-Flop CMOS using Synopsys Custom Compiler.

This repository contains a python script which converts a Boolean Expression to a .sim file.

FuzzyACOR-Algorithm (Adaptive fuzzy metaheuristic based optimisation algorithm)

FuzzyMSFLA-Algorithm (Fuzzy adaptive optimisation method)

This project demonstrates the complete design, layout, simulation, and verification of a **CMOS Inverter** using the **Electric VLSI Design Tool**.

This repository contains all the experiments which I have done on LTSpice software for the VLSI Design course.

This repository contains the design, simulation, and performance evaluation of a CMOS NAND Gate using Cadence Virtuoso. The project highlights the design principles and operational characteristics of a fundamental digital logic gate implemented with CMOS technology.

Using a pulse wave as an input referencing as clock we try to generate three different pulses having different pulse width

Final Transmission Line Analysis Project for my UW Applied Electrodynamics course which implements a Transmission Line representation of a CMOS circuit using the circuit simulator program, LTSpice.

Designed and simulated all fundamental and universal CMOS logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) using the Electric VLSI Design Tool. This project includes schematic design, DRC-clean layouts, ALS simulation, and waveform analysis.

CMOS preprocessor design based on neural networks for detecting heart rate.

This project showcases the design and simulation of a 7T MCPL SRAM using adiabatic logic for low-power efficiency, developed for ECL 312 at IIIT Nagpur. It compares the 6T and 7T SRAM designs in terms of power, energy, and stability, with simulations done in WinSpice and Microwind.

High-performance 8-bit Manchester adder optimized for accumulator applications using hybrid CMOS/PTL logic. Features transmission gate carry chain, post-layout power analysis, and comprehensive comparison with other adder architectures.