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schematic-design

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Designed and simulated all fundamental and universal CMOS logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) using the Electric VLSI Design Tool. This project includes schematic design, DRC-clean layouts, ALS simulation, and waveform analysis.

  • Updated May 10, 2025

This repository explores the design of a seven-segment display decoder focused on segment 'e'. It compares various logic design methods—including sum of products, product of sums, and NOR gate implementations—using Boolean algebra and Karnaugh maps. The study concludes that the NOR gate circuit is the most efficient, requiring only three NOR gates,

  • Updated Aug 21, 2025

This repository documents three parts of a practical electronics and circuit analysis project using both hardware and CAD tools. Part A investigates RLC circuit behavior—such as rise/fall time, phase shift, and resonance—using the D3000 board and NI Multisim. Results show that Multisim closely aligns with theoretical values due to real-world compon

  • Updated Aug 22, 2025
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