An innovative Verilog-A compiler

Verilog-A simulation models

A simple MOSFET model with only 5-DC-parameters for circuit simulation

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed at UC Berkeley

defunct. use repo on savannah

A digital genetic algorithm processor

A fast generative model for stochastic memory cells

A Verilog-AMS parser for .NET

Generates verilogA testbench (stimulus and waveforms) for verification of analog IPs (VLSI design)

Python Automatic Device Model Synthesizer

converts a stg (.g file generated by workcraft) to a verilogA model

Compact model for light propagation simulation in fNIRS systems

Language support in Visual Studio Code for VerilogA