🖥️ A collection of SystemVerilog modules and Assembly programs. This repo includes examples of decoders, encoders, binary adders, and interactive games such as Guessing Game implemented in hardware description and assembly languages, illustrating practical applications in digital systems and microprocessor interfacing.

Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.

Its my midterm project for Logic Circuit Course

Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur

A 32-bit Kogge-Stone Adder is implemented in this design.

An efficient multiplier and Accumulator (MAC) unit to do operations like multiplication & addition on numbers stored in RAM unit attached to it.

explore different implementations of adders and study their characteristics.

Collection of Adders such as Ripple Carry and Carry Look Ahead

Parametrized Verilog implementation of different architectures of adder / subtractor circuits.

A 32-bit Signed Vedic Multiplier created using Verilog HDL utilising Vedic Mathematic Sutras formed using Carry Lookahead Adders as the basic building blocks.

Designing a 4-bit Carry Lookahead Adder using eSim

A Built in Self Test (BIST) controller is created in Verilog HDL to test a 6-bit Carry Lookahead Adder (CLA) utilising a 4-bit Signature Output Response Analyser (ORA).

Verilog Mini Projects

32 bits CLA(Carry Lookahead Adder) and ALU RTL and verification. 32位块间超前的超前进位加法器及ALU设计与验证

Carry-Lookahead 16-bits Adder (CLA16) computes sums by rapidly determining carry bits through parallel processing.

Computer Architecture - Practical Solution with Quartus - Sharif University of Technology

Implementation of the Carry look ahead adder algorihtm, and parallizing the algorithm using OpenMP libriries

This repository contain CAO algorithms implemented in C language.

Verilog for low delay 8-bit CLA with 4-bit lookahead circuits

Progetti di Elettronica Digitale 2021.