Hardware designs modelled with verilog
This is an implementation of a simple CPU in Logisim and Verilog.
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
A Datapath design which able to execute store operation as memory instruction, substraction and or operations as arithmetic instruction by Logisim. Additional explanations in readme.
VHDL register file with generic bitwidth, number of global register, number of windows, and number of registers per window.
Processor VHDL 💾 assignments for module: CSU22022
This is a 16-bit R-type instruction processor with register file, UAL, and instruction memory (RAM). Ideal for learning about processor design, it supports 8 arithmetic and logic operations and provides a starting point for building more complex designs.
16 bit processor designed in logisim
Computer Architecture - Practical Solution with Quartus - Sharif University of Technology
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