All the projects and assignments done as part of VLSI course.

Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.

explore different implementations of adders and study their characteristics.

work done as part of VLSI Design practice course

Digital System Design Lab Codes using Verilog

Parametrized Verilog implementation of different architectures of adder / subtractor circuits.

Computer Architecture - Practical Solution with Quartus - Sharif University of Technology

An 4-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.

My VHDL Codes during EE214 (Digital Lab) Spring 2020-21

Useful VHDL scripts for hardware description.

Progetto di Elettronica Digitale AA 2022-2023

Design and simulation of 16-bit Ripple Carry and Weinberger Adders using Cadence Virtuoso. Includes full adder modeling, schematic creation, waveform analysis, and detailed delay-power comparison.

Layout of 4bit Ripple Carry Adder formed using CMOS logic in gpdk180nm technology node done in Cadence Virtuoso with no DRC and LVS errors.

Digital Circuits: Ripple Carry Adder.

All the various adders in Verilog!

Performance Analysis of a 4-bit Ripple Carry Adder (RCA) formed using Static CMOS, Transmission Gate, NMOS Pass Transistor Logic at gpdk 180nm Technology node.

A repository for some modules I made while learning Verilog

Design and Verification of a complete multi-digit BCD adder, using both ripple-carry and carry look-ahead architectures. Design relied on modularity and hierarchy, while validation was implemented through behavioral reference model.

Implementation of four Ripple-Carry Quantum Adders with Qiskit.

A 4-bit ripple-carry adder-subtractor created in Logisim.