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Firtool Release 1.77.0
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@jackkoenig jackkoenig released this 12 Jul 21:54
firtool-1.77.0
2f8ba28
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GPG key ID: B5690EEEBB952194
Learn about vigilant mode.

What's Changed

  • [FIRRTL][NFC] Move IST -> FieldRef to FIRRTLUtils.h by @dtzSiFive in #7135
  • [Docs][LTL] Add SVA Encodings to LTL rationale by @dobios in #7131
  • [FIRRTL] Enable Wire Elimination by @darthscsi in #7073
  • Capitalize Mode in github workflow. by @darthscsi in #7140
  • [ExportVerilog][HW] Introduce HWEmittableModuleLike interface and use it for Prepare, NFC by @uenoku in #7004
  • [FIRRTL][InferResets] Learn how to trace through nodes. by @dtzSiFive in #7141
  • [Moore] Introduce RefType and tweak the related ops. by @hailongSun2000 in #7095
  • [ExportVerilog] Support sv.func.* op emission by @uenoku in #7015
  • [Docs] Update Python bindings pip instructions by @leonardt in #7147
  • [Ibis] Divorce symbol and actual names in class and container ops by @mortbopet in #7123
  • [FIRRTL] Support abstract reset in RWProbeOp by @dtzSiFive in #7136
  • [FIRRTL] Cast to AnyRefType for metadata output port. by @mikeurbach in #7149
  • [Handshake] Fix canonicalizer not going through rewriter for RAUW. by @dtzSiFive in #7052
  • [MooreToCore] Add conversion support for module and instance. by @cepheus69 in #7132
  • [FIRRTL] Emulate tap-as-passive for no-ref-ports option. by @dtzSiFive in #7109
  • [FIRRTL][Parser] Never use forceable by @dtzSiFive in #7137
  • [FIRRTL] Bump minimum to 2.0.0, remove partial connect by @seldridge in #5075
  • [FIRRTL][Metadata] Add the path to the DUT, in the SiFive metadata class. by @prithayan in #7156
  • [firtool] Remove LTLToCore pass from verification-flavor=immediate pipeline by @dobios in #7157
  • [Moore] Introduce Mem2Reg to eliminate local variables by @hailongSun2000 in #7082
  • [Moore] Add the SimplifyProcedures pass. by @hailongSun2000 in #7161
  • [Sim] Add DPI func/call and lowering by @uenoku in #7042
  • [ExportVerilog] Avoid using interface pass for PrepareForEmission, NFCI by @uenoku in #7168
  • [FIRRTL] Add DPI call intrinsic and lowering pass by @uenoku in #7139
  • [FIRRTL][ExportVerilog] Emit integers on DPI function as two state C-compatible types and clarify ABI by @uenoku in #7163
  • [LowerDPI] Defer deletion of call ops to prevent inavlid access. by @fzi-hielscher in #7170
  • [FIRRTL] Add a new op interface for combinational loop detection. by @prithayan in #7120
  • [NFC][ExportVerilog] Rename generated options member. by @fzi-hielscher in #7172
  • [Moore] Add evenOp to handle event controls. by @hailongSun2000 in #7154
  • [ImportVerilog][MooreToCore]Lower moore.namedConstant to hw.constant & hw.wire by @mingzheTerapines in #7122
  • Bump llvm by @uenoku in #7167
  • [LowerDPI] Refactor the lowering logic to a helper struct, NFC by @uenoku in #7176
  • [NFCI][Conversion] Refactor TableGen Pass includes by @fzi-hielscher in #7174
  • [NFCI][Calyx] Refactor TableGen Pass includes by @fzi-hielscher in #7182
  • [NFCI][Transforms] Refactor TableGen Pass includes by @fzi-hielscher in #7173
  • [FIRRTL] Output directory control for layers and modules by @rwy7 in #6971
  • [Verif] Add PrepareForFormal pass by @dobios in #7175
  • [FIRRTL] Add pass to specialize layers by @youngar in #7160
  • Fix paths in tests for windows builds by @rwy7 in #7185
  • Add missing header includes by @rwy7 in #7187
  • [NFCI][Comb][HW][Seq] Refactor TableGen Pass includes by @fzi-hielscher in #7180
  • [NFCI][ESI][Ibis][MSFT] Refactor TableGen Pass includes by @fzi-hielscher in #7179
  • [NFCI][LLHD][Moore][SV][Verif] Refactor TableGen Pass includes by @fzi-hielscher in #7183
  • [FIRRTL][ExpandWhens] Add StmtExprVisitor to Visitor and Support DPI intrinsic in ExpandWhens by @uenoku in #7177
  • [SimToSV] Fix DPICall lowering to use replaceOp by @uenoku in #7192
  • [NFCI][FIRRTL] Refactor TableGen Pass includes by @fzi-hielscher in #7178
  • [ExportVerilog] Fix two state type emission of aggregate types by @uenoku in #7189
  • [FIRRTL][SpecializeLayers] Update doc with proper attribute name by @youngar in #7199
  • [NFCI][DC][FSM][Handshake][Pipeline] Refactor TableGen Pass includes by @fzi-hielscher in #7181
  • [NFCI][OM][SSP][SystemC] Refactor TableGen Pass includes by @fzi-hielscher in #7184
  • [FIRRTL][SpecializeLayers] Fix incorrect CF leading to double free by @youngar in #7200
  • [firtool] Move SpecializeLayers before LowerLayers by @youngar in #7201
  • [FIRRTL][CheckCombLoops] Verify that detection works with region ops by @youngar in #7198
  • [HW] Move the CombDataFlow op interface from FIRRTL to HW by @prithayan in #7195
  • [FIRRTL][NFC] Fast-path removeAnnotations for operations having none. by @dtzSiFive in #7203
  • [FIRRTL] AnnotationSet cleanups by @youngar in #7205
  • [ESI][PyCDE] Callback service by @teqdruid in #7153
  • [Moore] Support unconnected behavior by @cepheus69 in #7202
  • [CI] Add a job to remove cache created by short integrations tests by @uenoku in #7214
  • [Moore] Fix the stacking fault caused by cast and remove unused headers by @hailongSun2000 in #7219
  • [FIRRTL] LHSType wrapper to indicate writable values. by @darthscsi in #7117
  • [FIRRTL] SpecializeLayers: fix race condition by @youngar in #7218
  • [HW] Clean up HWTypes, NFC by @uenoku in #7209
  • README.md: remove link to dead build by @youngar in #7222
  • [FIRRTL][Verif][LTL] Replace ltl.disable with an enable folded into verif.assert by @dobios in #7150
  • [LowerClass] Run path tracking sequentially by @uenoku in #7221
  • [ESI Runtime] Replace Cap'nProto with gRPC by @teqdruid in #7217
  • [ESI Runtime] Read ports now invoke callbacks by @teqdruid in #7186
  • [CI] Revert to working image and disable ESI runtime by @teqdruid in #7237
  • [FIRRTL] Allow layers under when and match. by @dtzSiFive in #7234
  • [ESI Runtime] Rename cmake targets, create full build one by @teqdruid in #7238
  • Bump LLVM by @girishpai in #7223
  • [FIRRTL] lower-layers.mlir: fix incorrect op name in test by @youngar in #7232
  • [Moore] Add extra class declaration for RefType. by @hailongSun2000 in #7244
  • [Interop] Use properties for inherent attributes. by @dtzSiFive in #7235
  • [ImportVerilog] Support Generate constructs by @angelzzzzz in #7243
  • [NFC][Seq] Remove unnecessary dependency of Seq on SV by @TaoBi22 in #7247
  • [NFC][SV] Remove unnecessary dependency of SV on Verif by @TaoBi22 in #7249
  • [Moore] Add LowerConcatRef pass to handle concat_ref. by @hailongSun2000 in #7216
  • [ESI Runtime][NFC] Incorporate RPC server into ESICppRuntime by @teqdruid in #7241
  • [ESI Runtime] Avoid using CIRCT_* cmake variables by @teqdruid in #7256
  • [FIRRTL][ResolvePaths] Fix detection of agg target if alias. by @dtzSiFive in #7257
  • [MooreToCore] Fix parse error for parameter by @mingzheTerapines in #7253
  • [FIRRTL] Ensure hierpath considers owning module in LowerClasses. by @mikeurbach in #7272
  • [Arc] Add VectorizeOp canonicalization by @elhewaty in #7146
  • [Moore] To make SVModule having a graph region. by @hailongSun2000 in #7258
  • [FIRRTL] Add input and output names to DPI intrinsic by @uenoku in #7265
  • [ESI Runtime] Load backends as plugins by @teqdruid in #7260
  • [PyCDE] Restrict slicing index widths to clog2(len) by @teqdruid in #7277
  • [FIRRTL] Fix use-after-free in InferReset by @darthscsi in #7273
  • [Moore] Add AssignedVarOp and canonicalization for VariableOp. by @hailongSun2000 in #7251
  • [ESI] Add read-side MMIO back by @teqdruid in #7282
  • [ESI] Make MMIO data 64-bit by @teqdruid in #7283
  • [FIRRTL][HW] Change default implementation of CombDataFlow and add it to DPI intrinsic by @uenoku in #7267
  • [FSM]New builders for StateOp and TransitionOp. by @HahaLan97 in #6991
  • CODEOWNERS: remove @dtzSiFive from most paths. by @dtzSiFive in #7288
  • [FIRRTL][ModuleInliner] Add a prefix to memory instances by @uenoku in #7279
  • [Moore] SymbolVisibility attribute support for SVModuleOp by @cepheus69 in #7278
  • [ESI] Add verify connections pass by @teqdruid in #7287
  • [Seq] Remove incorrect canonicalization by @uenoku in #7289
  • [RFC][Sim] Add format string type and format specifier ops by @fzi-hielscher in #7208
  • [NFC][HW] Fix parsing of nullary hw.triggered ops by @fzi-hielscher in #7291
  • [Arc] Keep just one parameter if it's given multiple times by @elhewaty in #7284
  • [HW] Specify llvm::SmallVector namespace. NFC. by @prithayan in #7293
  • [ImportVerilog] Distinguish the index up or down on the range selection. by @hailongSun2000 in #7280
  • [ImportVerilog] Fix the segmentation fault caused by the case statement. by @hailongSun2000 in #7295
  • [SV][Verif] Extract clocked verif ops in ExtractTestCode pass by @uenoku in #7296
  • [PyCDE][ESI] Manifest: add record about client by @teqdruid in #7299
  • Move ResetType under the sv namespace by @rwy7 in #7300
  • [Verif] Add verif.bmc operation by @TaoBi22 in #7263
  • Allow firrtl hardware ops under sv.ifdef by @rwy7 in #7309
  • [ESI] MMIO read service implementation in PyCDE by @teqdruid in #7306
  • [ESI][PyCDE] ChannelSignal: add buffer method by @teqdruid in #7310
  • [ESI] Remove last references to capnp by @teqdruid in #7315
  • Revert "[FIRRTL] Enable Wire Elimination (#7073)" by @jackkoenig in #7311
  • [SV] Add Intermediary Assert Op for better enable polarity flip by @dobios in #7302

Full Changelog: firtool-1.76.0...firtool-1.77.0

Contributors

seldridge, mikeurbach, and 20 other contributors
Assets 20
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