v1.10

Tested mainly with Vivado 2019.2 and 2020.2.

Contains Ethernet-based example designs for:

• Xilinx KC705 eval board
• Xilinx KCU105 eval board
• Xilinx VCU118 eval board
• Xilinx ZCU102 eval board
• PC053a

And PCIe-based example designs for:

• HiTech Global K800
• Xilinx VCU118 eval board

Core

Bugfixes

• AXI transport interface (ipbus_transport_axi): Simulation dep files fixed [issue #198]

Boards, example designs and utilities

• Standardise the clock constraints across example designs, taking into account [Issue #I07]

Backward-incompatible changes

• Exposed rarp_enable signal on ethernet example infra blocks [PR #197 and #200]
• Enclustra boards moved to the ipbus-contrib GitHub organisation.

v1.9

Tested mainly with Vivado 2018.3 and 2019.2.

Contains Ethernet-based example designs for:

• Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
• Xilinx KC705 eval board
• Xilinx KCU105 eval board
• Xilinx VCU118 eval board
• Xilinx ZCU102 eval board
• PC053a

And PCIe-based example designs for:

• HiTech Global K800
• Xilinx VCU118 eval board

Bugfixes

• Xilinx example projects: Fix typo ipbb add git URL in README
• Updated dependency files to be compatible with latest tags of IPBB (i.e. dev/2021f) [issue #191]

Minor improvements¶

• ICAP slave: Added description field to address table [issue #180]

v1.8

Tested mainly with Vivado 2018.3 and 2019.2.

Contains Ethernet-based example designs for:

• Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
• Xilinx KC705 eval board
• Xilinx KCU105 eval board
• Xilinx VCU118 eval board
• Xilinx ZCU102 eval board
• PC053a

And PCIe-based example designs for:

• HiTech Global K800
• Xilinx VCU118 eval board

Core

Bugfixes

• PCIe: Corrected minor syntax issue in ipbus_transport_multibuffer_if.vhd that Vivado flags as a critical warning [issue #164]

Slaves

New slaves

For Xilinx ICAP and IPROG primitives, and an IPbus slave that behaves as a master to AXI4-lite bus (courtesy of Jeroen Hegeman, all files under components/ipbus_util):

slave	details
ipbus_icap_x7	ICAP (7-series devices) [issue #161]
ipbus_icap_us_usp	ICAP (Ultrascale & Ultrascale+) [issue #161]
ipbus_iprog_x7	IPROG (7-series devices) [issue #161]
ipbus_iprog_us_usp	IPROG (Ultrascale & Ultrascale+) [issue #161]
ipbus_axi4lite_master	Master to an AXI4lite bus [issue #168]

The ICAP slaves support register reads and writes, as well as FPGA reconfiguration from a configurable base address. The IPROG slaves support FPGA reconfiguration from a configurable base address.

Bugfixes

• Added missing dependency to ipbus_freq_ctr.dep [issue #171]
• Removed the id attribute from the root node of all address table files (since not used by uHAL) [issue #170]

Boards, example designs and utilities

Added a 7-series SGMII Ethernet block (tested on the VC707 development board) [issue #173]

v1.7

Tested mainly with Vivado 2018.3 and 2019.2.

Contains Ethernet-based example designs for:

• Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
• Xilinx KC705 eval board
• Xilinx KCU105 eval board
• Xilinx VCU118 eval board
• Xilinx ZCU102 eval board
• PC053a

And PCIe-based example designs for:

• HiTech Global K800
• Xilinx VCU118 eval board

Core

Improvements

• Transactor arbiter removed from main dependency file for ipbus_core [issue #140]
• Ethernet/UDP transport interface: Added new depfile, ipbus_ctrl.dep under components/ipbus_util that references ipbus_ctrl.vhd and all its dependencies [issue #140]
• AXI transport interface (ipbus_transport_axi): Simulation testbench files removed from main dependency file [issue #136]

Bugfixes

• PCIe: Resolved error during XDMA IP core upgrade that affected Ultrascale+ designs in Vivado 2019.2 [issue #156]
• The new Ultrascale+ XDMA XCI file works with Vivado 2018.1 onwards

Slaves

New slaves

For Xilinx SYSMON and DNA primitives (all files under components/ipbus_util):

slave	details
ipbus_sysmon_x7	SYSMON (7-series devices) [issue #144]
ipbus_sysmon_us	SYSMON (Ultrascale devices) [issue #144]
ipbus_sysmon_usp	SYSMON (Ultrascale+ devices) [issue #144]
ipbus_device_dna_us_usp	DNA (Ultrascale & Ultrascale+) [issue #151]

Other improvements

• Added dependency files for all slaves that have more dependencies than just the ipbus package [issue #142]. Specifically:
  • ipbus_ctrlreg_v
  • ipbus_drp_bridge
  • ipbus_emac_hostbus
  • ipbus_reg_v
  • ipbus_roreg_v

Backward-incompatible changes

• ipbus_syncreg_v: Renamed dependency file from syncreg_v.dep to ipbus_syncreg_v.dep (for consistency with other slave dependency files) [issue #141]
• freq_ctr_div: Renamed VHDL file from ipbus_freq_ctr_div.vhd to freq_ctr_div.vhd [issue #109]
• drp_decl: Increased address width from 9 to 16 bits [issue #150]
• ipbus_oob_test: Removed, since no longer used [issue #148]

Boards, example designs and utilities

Added a preliminary implementation of an example design in which packets of IPbus transactions are sent and received over the PS-PL interface, as well as over an AXI chip-to-chip link. Board: ZCU102 [issue #133]

Backward-incompatible changes

• trans_buffer and trans_buffer_test: Moved from components/ipbus_slaves to components/ipbus_util (since not a slave) [issue #148]
  Bugfixes

• Fixed problems in simulation dependency files for a few example designs [issue #154]