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FE310-based boards: transition from pinmux to pinctrl #44068

Merged
merged 7 commits into from
Mar 24, 2022
Merged

FE310-based boards: transition from pinmux to pinctrl #44068

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357cdfc
drivers: pinctrl: add SiFive pinctrl driver
fkokosinski Mar 22, 2022
edf2cfb
boards: hifive1: add pinctrl configuration for hifive1 board
fkokosinski Mar 22, 2022
b932ece
boards: hifive1_revb: add pinctrl configuration for hifive1_revb board
fkokosinski Mar 22, 2022
d30415b
boards: qemu_riscv32: add pinctrl configuration for qemu_riscv32_xip
fkokosinski Mar 22, 2022
f132c59
boards: FE310-based boards: transition to pinctrl driver
fkokosinski Mar 22, 2022
ed0637c
drivers: pinmux: remove SiFive pinmux driver
fkokosinski Mar 22, 2022
18f66f5
soc: riscv: sifive-freedom: fix SYS_CLOCK_HW_CYCLES_PER_SEC value
fkokosinski Mar 23, 2022
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4 changes: 0 additions & 4 deletions boards/riscv/hifive1/CMakeLists.txt
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79 changes: 79 additions & 0 deletions boards/riscv/hifive1/hifive1-pinctrl.dtsi
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Original file line number Diff line number Diff line change
@@ -0,0 +1,79 @@
/*
* Copyright (c) 2022 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <dt-bindings/pinctrl/sifive-pinctrl.h>

&pinctrl {
/* UART0 */
uart0_rx_default: uart0_rx_default {
pinmux = <16 SIFIVE_PINMUX_IOF0>;
};
uart0_tx_default: uart0_tx_default {
pinmux = <17 SIFIVE_PINMUX_IOF0>;
};
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/* SPI1 */
spi1_cs0_default: spi1_cs0_default {
pinmux = <2 SIFIVE_PINMUX_IOF0>;
};
spi1_mosi_default: spi1_mosi_default {
pinmux = <3 SIFIVE_PINMUX_IOF0>;
};
spi1_miso_default: spi1_miso_default {
pinmux = <4 SIFIVE_PINMUX_IOF0>;
};
spi1_sck_default: spi1_sck_default {
pinmux = <5 SIFIVE_PINMUX_IOF0>;
};
spi1_cs2_default: spi1_cs2_default {
pinmux = <9 SIFIVE_PINMUX_IOF0>;
};
spi1_cs3_default: spi1_cs3_default {
pinmux = <10 SIFIVE_PINMUX_IOF0>;
};

/* PWM0 */
pwm0_0_default: pwm0_0_default {
pinmux = <0 SIFIVE_PINMUX_IOF1>;
};
pwm0_1_default: pwm0_1_default {
pinmux = <1 SIFIVE_PINMUX_IOF1>;
};
pwm0_2_default: pwm0_2_default {
pinmux = <2 SIFIVE_PINMUX_IOF1>;
};
pwm0_3_default: pwm0_3_default {
pinmux = <3 SIFIVE_PINMUX_IOF1>;
};

/* PWM1 */
pwm1_0_default: pwm1_0_default {
pinmux = <20 SIFIVE_PINMUX_IOF1>;
};
pwm1_1_default: pwm1_1_default {
pinmux = <19 SIFIVE_PINMUX_IOF1>;
};
pwm1_2_default: pwm1_2_default {
pinmux = <21 SIFIVE_PINMUX_IOF1>;
};
pwm1_3_default: pwm1_3_default {
pinmux = <22 SIFIVE_PINMUX_IOF1>;
};

/* PWM2 */
pwm2_0_default: pwm2_0_default {
pinmux = <10 SIFIVE_PINMUX_IOF1>;
};
pwm2_1_default: pwm1_1_default {
pinmux = <11 SIFIVE_PINMUX_IOF1>;
};
pwm2_2_default: pwm2_2_default {
pinmux = <12 SIFIVE_PINMUX_IOF1>;
};
pwm2_3_default: pwm2_3_default {
pinmux = <13 SIFIVE_PINMUX_IOF1>;
};
};
10 changes: 10 additions & 0 deletions boards/riscv/hifive1/hifive1.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@
/dts-v1/;

#include <riscv32-fe310.dtsi>
#include "hifive1-pinctrl.dtsi"

/ {
model = "SiFive HiFive 1";
Expand Down Expand Up @@ -46,6 +47,8 @@
status = "okay";
current-speed = <115200>;
clock-frequency = <16000000>;
pinctrl-0 = <&uart0_rx_default &uart0_tx_default>;
pinctrl-names = "default";
};

&uart1 {
Expand All @@ -70,6 +73,9 @@
&spi1 {
status = "okay";
clock-frequency = <16000000>;
pinctrl-0 = <&spi1_cs0_default &spi1_cs2_default &spi1_cs3_default
&spi1_mosi_default &spi1_miso_default &spi1_sck_default>;
pinctrl-names = "default";
};

&spi2 {
Expand All @@ -85,9 +91,13 @@
&pwm1 {
status = "okay";
clock-frequency = <16000000>;
pinctrl-0 = <&pwm1_1_default &pwm1_2_default &pwm1_3_default>;
pinctrl-names = "default";
};

&pwm2 {
status = "okay";
clock-frequency = <16000000>;
pinctrl-0 = <&pwm2_1_default &pwm2_2_default &pwm2_3_default>;
pinctrl-names = "default";
};
3 changes: 1 addition & 2 deletions boards/riscv/hifive1/hifive1_defconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,7 @@ CONFIG_UART_SIFIVE=y
CONFIG_UART_SIFIVE_PORT_0=y
CONFIG_UART_CONSOLE=y
CONFIG_PLIC=y
CONFIG_PINMUX=y
CONFIG_PINMUX_SIFIVE=y
CONFIG_PINCTRL=y
CONFIG_RISCV_MACHINE_TIMER=y
CONFIG_GPIO=y
CONFIG_GPIO_SIFIVE=y
Expand Down
54 changes: 0 additions & 54 deletions boards/riscv/hifive1/pinmux.c
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4 changes: 0 additions & 4 deletions boards/riscv/hifive1_revb/CMakeLists.txt
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This file was deleted.

87 changes: 87 additions & 0 deletions boards/riscv/hifive1_revb/hifive1_revb-pinctrl.dtsi
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Original file line number Diff line number Diff line change
@@ -0,0 +1,87 @@
/*
* Copyright (c) 2022 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <dt-bindings/pinctrl/sifive-pinctrl.h>

&pinctrl {
/* UART0 */
uart0_rx_default: uart0_rx_default {
pinmux = <16 SIFIVE_PINMUX_IOF0>;
};
uart0_tx_default: uart0_tx_default {
pinmux = <17 SIFIVE_PINMUX_IOF0>;
};

/* SPI1 */
spi1_cs0_default: spi1_cs0_default {
pinmux = <2 SIFIVE_PINMUX_IOF0>;
};
spi1_mosi_default: spi1_mosi_default {
pinmux = <3 SIFIVE_PINMUX_IOF0>;
};
spi1_miso_default: spi1_miso_default {
pinmux = <4 SIFIVE_PINMUX_IOF0>;
};
spi1_sck_default: spi1_sck_default {
pinmux = <5 SIFIVE_PINMUX_IOF0>;
};
spi1_cs2_default: spi1_cs2_default {
pinmux = <9 SIFIVE_PINMUX_IOF0>;
};
spi1_cs3_default: spi1_cs3_default {
pinmux = <10 SIFIVE_PINMUX_IOF0>;
};

/* PWM0 */
pwm0_0_default: pwm0_0_default {
pinmux = <0 SIFIVE_PINMUX_IOF1>;
};
pwm0_1_default: pwm0_1_default {
pinmux = <1 SIFIVE_PINMUX_IOF1>;
};
pwm0_2_default: pwm0_2_default {
pinmux = <2 SIFIVE_PINMUX_IOF1>;
};
pwm0_3_default: pwm0_3_default {
pinmux = <3 SIFIVE_PINMUX_IOF1>;
};

/* PWM1 */
pwm1_0_default: pwm1_0_default {
pinmux = <20 SIFIVE_PINMUX_IOF1>;
};
pwm1_1_default: pwm1_1_default {
pinmux = <19 SIFIVE_PINMUX_IOF1>;
};
pwm1_2_default: pwm1_2_default {
pinmux = <21 SIFIVE_PINMUX_IOF1>;
};
pwm1_3_default: pwm1_3_default {
pinmux = <22 SIFIVE_PINMUX_IOF1>;
};

/* PWM2 */
pwm2_0_default: pwm2_0_default {
pinmux = <10 SIFIVE_PINMUX_IOF1>;
};
pwm2_1_default: pwm1_1_default {
pinmux = <11 SIFIVE_PINMUX_IOF1>;
};
pwm2_2_default: pwm2_2_default {
pinmux = <12 SIFIVE_PINMUX_IOF1>;
};
pwm2_3_default: pwm2_3_default {
pinmux = <13 SIFIVE_PINMUX_IOF1>;
};

/* I2C0 */
i2c0_0_default: i2c0_0_default {
pinmux = <12 SIFIVE_PINMUX_IOF0>;
};
i2c0_1_default: i2c0_1_default {
pinmux = <13 SIFIVE_PINMUX_IOF0>;
};
};
5 changes: 5 additions & 0 deletions boards/riscv/hifive1_revb/hifive1_revb.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@

#include <riscv32-fe310.dtsi>
#include <dt-bindings/i2c/i2c.h>
#include "hifive1_revb-pinctrl.dtsi"

/ {
model = "SiFive HiFive 1 Rev B";
Expand Down Expand Up @@ -78,6 +79,8 @@
status = "okay";
current-speed = <115200>;
clock-frequency = <16000000>;
pinctrl-0 = <&uart0_rx_default &uart0_tx_default>;
pinctrl-names = "default";
};

&uart1 {
Expand Down Expand Up @@ -131,4 +134,6 @@ arduino_i2c: &i2c0 {
label = "I2C_0";
input-frequency = <16000000>;
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_0_default &i2c0_1_default>;
pinctrl-names = "default";
};
3 changes: 1 addition & 2 deletions boards/riscv/hifive1_revb/hifive1_revb_defconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,7 @@ CONFIG_RISCV_MACHINE_TIMER=y
CONFIG_PLIC=y
CONFIG_GPIO=y
CONFIG_GPIO_SIFIVE=y
CONFIG_PINMUX=y
CONFIG_PINMUX_SIFIVE=y
CONFIG_PINCTRL=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_SIFIVE=y
Expand Down
47 changes: 0 additions & 47 deletions boards/riscv/hifive1_revb/pinmux.c
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This file was deleted.

17 changes: 17 additions & 0 deletions boards/riscv/qemu_riscv32/qemu_riscv32_xip-pinctrl.dtsi
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Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
/*
* Copyright (c) 2022 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <dt-bindings/pinctrl/sifive-pinctrl.h>

&pinctrl {
/* UART0 */
uart0_rx_default: uart0_rx_default {
pinmux = <16 SIFIVE_PINMUX_IOF0>;
};
uart0_tx_default: uart0_tx_default {
pinmux = <17 SIFIVE_PINMUX_IOF0>;
};
};
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