boards: FE310-based boards: transition to pinctrl driver

This commit makes the transition from the pinmux driver to the pinctrl driver. It also modifies UART, SPI and I2C drivers used in FE310-based boards to use the new pinctrl API. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
zephyrproject-rtos · carlescufi · Mar 24, 2022 · Mar 22, 2022 · Mar 22, 2022 · Mar 22, 2022
commit f132c59c1365c0f166766fa94f15137cef49e45f
diff --git a/boards/riscv/hifive1/CMakeLists.txt b/boards/riscv/hifive1/CMakeLists.txt
diff --git a/boards/riscv/hifive1/hifive1.dts b/boards/riscv/hifive1/hifive1.dts
@@ -4,6 +4,7 @@
 /dts-v1/;
 
 #include <riscv32-fe310.dtsi>
+#include "hifive1-pinctrl.dtsi"
 
 / {
 	model = "SiFive HiFive 1";
@@ -46,6 +47,8 @@
 	status = "okay";
 	current-speed = <115200>;
 	clock-frequency = <16000000>;
+	pinctrl-0 = <&uart0_rx_default &uart0_tx_default>;
+	pinctrl-names = "default";
 };
 
 &uart1 {
@@ -70,6 +73,9 @@
 &spi1 {
 	status = "okay";
 	clock-frequency = <16000000>;
+	pinctrl-0 = <&spi1_cs0_default &spi1_cs2_default &spi1_cs3_default
+		     &spi1_mosi_default &spi1_miso_default &spi1_sck_default>;
+	pinctrl-names = "default";
 };
 
 &spi2 {
@@ -85,9 +91,13 @@
 &pwm1 {
 	status = "okay";
 	clock-frequency = <16000000>;
+	pinctrl-0 = <&pwm1_1_default &pwm1_2_default &pwm1_3_default>;
+	pinctrl-names = "default";
 };
 
 &pwm2 {
 	status = "okay";
 	clock-frequency = <16000000>;
+	pinctrl-0 = <&pwm2_1_default &pwm2_2_default &pwm2_3_default>;
+	pinctrl-names = "default";
 };
diff --git a/boards/riscv/hifive1/hifive1_defconfig b/boards/riscv/hifive1/hifive1_defconfig
@@ -9,8 +9,7 @@ CONFIG_UART_SIFIVE=y
 CONFIG_UART_SIFIVE_PORT_0=y
 CONFIG_UART_CONSOLE=y
 CONFIG_PLIC=y
-CONFIG_PINMUX=y
-CONFIG_PINMUX_SIFIVE=y
+CONFIG_PINCTRL=y
 CONFIG_RISCV_MACHINE_TIMER=y
 CONFIG_GPIO=y
 CONFIG_GPIO_SIFIVE=y

diff --git a/boards/riscv/hifive1/pinmux.c b/boards/riscv/hifive1/pinmux.c
diff --git a/boards/riscv/hifive1_revb/CMakeLists.txt b/boards/riscv/hifive1_revb/CMakeLists.txt
diff --git a/boards/riscv/hifive1_revb/hifive1_revb.dts b/boards/riscv/hifive1_revb/hifive1_revb.dts
@@ -5,6 +5,7 @@
 
 #include <riscv32-fe310.dtsi>
 #include <dt-bindings/i2c/i2c.h>
+#include "hifive1_revb-pinctrl.dtsi"
 
 / {
 	model = "SiFive HiFive 1 Rev B";
@@ -78,6 +79,8 @@
 	status = "okay";
 	current-speed = <115200>;
 	clock-frequency = <16000000>;
+	pinctrl-0 = <&uart0_rx_default &uart0_tx_default>;
+	pinctrl-names = "default";
 };
 
 &uart1 {
@@ -131,4 +134,6 @@ arduino_i2c: &i2c0 {
 	label = "I2C_0";
 	input-frequency = <16000000>;
 	clock-frequency = <100000>;
+	pinctrl-0 = <&i2c0_0_default &i2c0_1_default>;
+	pinctrl-names = "default";
 };
diff --git a/boards/riscv/hifive1_revb/hifive1_revb_defconfig b/boards/riscv/hifive1_revb/hifive1_revb_defconfig
@@ -5,8 +5,7 @@ CONFIG_RISCV_MACHINE_TIMER=y
 CONFIG_PLIC=y
 CONFIG_GPIO=y
 CONFIG_GPIO_SIFIVE=y
-CONFIG_PINMUX=y
-CONFIG_PINMUX_SIFIVE=y
+CONFIG_PINCTRL=y
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_SIFIVE=y

diff --git a/boards/riscv/hifive1_revb/pinmux.c b/boards/riscv/hifive1_revb/pinmux.c
diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_xip.dts b/boards/riscv/qemu_riscv32/qemu_riscv32_xip.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include <riscv32-fe310.dtsi>
+#include "qemu_riscv32_xip-pinctrl.dtsi"
 
 / {
 	model = "SiFive HiFive 1";
@@ -29,6 +30,8 @@
 	status = "okay";
 	current-speed = <115200>;
 	clock-frequency = <16000000>;
+	pinctrl-0 = <&uart0_rx_default &uart0_tx_default>;
+	pinctrl-names = "default";
 };
 
 &uart1 {

diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_xip_defconfig b/boards/riscv/qemu_riscv32/qemu_riscv32_xip_defconfig
@@ -9,8 +9,7 @@ CONFIG_UART_SIFIVE=y
 CONFIG_UART_SIFIVE_PORT_0=y
 CONFIG_UART_CONSOLE=y
 CONFIG_PLIC=y
-CONFIG_PINMUX=y
-CONFIG_PINMUX_SIFIVE=y
+CONFIG_PINCTRL=y
 CONFIG_RISCV_MACHINE_TIMER=y
 CONFIG_GPIO=y
 CONFIG_GPIO_SIFIVE=y

diff --git a/drivers/pwm/pwm_sifive.c b/drivers/pwm/pwm_sifive.c
@@ -12,6 +12,7 @@ LOG_MODULE_REGISTER(pwm_sifive, CONFIG_PWM_LOG_LEVEL);
 
 #include <sys/sys_io.h>
 #include <device.h>
+#include <drivers/pinctrl.h>
 #include <drivers/pwm.h>
 
 /* Macros */
@@ -52,6 +53,7 @@ struct pwm_sifive_cfg {
 	uint32_t base;
 	uint32_t f_sys;
 	uint32_t cmpwidth;
+	const struct pinctrl_dev_config *pcfg;
 };
 
 /* Helper Functions */
@@ -71,6 +73,14 @@ static inline void sys_set_mask(mem_addr_t addr, uint32_t mask, uint32_t value)
 static int pwm_sifive_init(const struct device *dev)
 {
 	const struct pwm_sifive_cfg *config = dev->config;
+#ifdef CONFIG_PINCTRL
+	int ret;
+
+	ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		return ret;
+	}
+#endif
 
 	/* When pwms == pwmcmp0, reset the counter */
 	sys_set_bit(PWM_REG(config, REG_PWMCFG), SF_PWMZEROCMP);
@@ -223,11 +233,13 @@ static const struct pwm_driver_api pwm_sifive_api = {
 };
 
 #define PWM_SIFIVE_INIT(n)	\
+	PINCTRL_DT_INST_DEFINE(n);	\
 	static struct pwm_sifive_data pwm_sifive_data_##n;	\
 	static const struct pwm_sifive_cfg pwm_sifive_cfg_##n = {	\
 			.base = DT_INST_REG_ADDR(n),	\
 			.f_sys = DT_INST_PROP(n, clock_frequency),  \
 			.cmpwidth = DT_INST_PROP(n, sifive_compare_width), \
+			.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),	\
 		};	\
 	DEVICE_DT_INST_DEFINE(n,	\
 			    pwm_sifive_init,	\

diff --git a/drivers/serial/uart_sifive.c b/drivers/serial/uart_sifive.c
@@ -13,6 +13,7 @@
 #include <kernel.h>
 #include <arch/cpu.h>
 #include <drivers/uart.h>
+#include <drivers/pinctrl.h>
 
 #define RXDATA_EMPTY   (1 << 31)   /* Receive FIFO Empty */
 #define RXDATA_MASK    0xFF        /* Receive Data Mask */
@@ -47,13 +48,14 @@ typedef void (*irq_cfg_func_t)(void);
 #endif
 
 struct uart_sifive_device_config {
-	uintptr_t   port;
-	uint32_t       sys_clk_freq;
-	uint32_t       baud_rate;
-	uint32_t       rxcnt_irq;
-	uint32_t       txcnt_irq;
+	uintptr_t	port;
+	uint32_t	sys_clk_freq;
+	uint32_t	baud_rate;
+	uint32_t	rxcnt_irq;
+	uint32_t	txcnt_irq;
+	const struct	pinctrl_dev_config *pcfg;
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
-	irq_cfg_func_t cfg_func;
+	irq_cfg_func_t	cfg_func;
 #endif
 };
 
@@ -318,6 +320,9 @@ static int uart_sifive_init(const struct device *dev)
 {
 	const struct uart_sifive_device_config * const cfg = dev->config;
 	volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
+#ifdef CONFIG_PINCTRL
+	int ret;
+#endif
 
 	/* Enable TX and RX channels */
 	uart->txctrl = TXCTRL_TXEN | CTRL_CNT(cfg->txcnt_irq);
@@ -334,6 +339,13 @@ static int uart_sifive_init(const struct device *dev)
 	cfg->cfg_func();
 #endif
 
+#ifdef CONFIG_PINCTRL
+	ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		return ret;
+	}
+#endif
+
 	return 0;
 }
 
@@ -367,12 +379,15 @@ static struct uart_sifive_data uart_sifive_data_0;
 static void uart_sifive_irq_cfg_func_0(void);
 #endif
 
+PINCTRL_DT_INST_DEFINE(0);
+
 static const struct uart_sifive_device_config uart_sifive_dev_cfg_0 = {
 	.port         = DT_INST_REG_ADDR(0),
 	.sys_clk_freq = DT_INST_PROP(0, clock_frequency),
 	.baud_rate    = DT_INST_PROP(0, current_speed),
 	.rxcnt_irq    = CONFIG_UART_SIFIVE_PORT_0_RXCNT_IRQ,
 	.txcnt_irq    = CONFIG_UART_SIFIVE_PORT_0_TXCNT_IRQ,
+	.pcfg	      = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	.cfg_func     = uart_sifive_irq_cfg_func_0,
 #endif
@@ -385,6 +400,7 @@ DEVICE_DT_INST_DEFINE(0,
 		    PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY,
 		    (void *)&uart_sifive_driver_api);
 
+
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 static void uart_sifive_irq_cfg_func_0(void)
 {
@@ -406,12 +422,15 @@ static struct uart_sifive_data uart_sifive_data_1;
 static void uart_sifive_irq_cfg_func_1(void);
 #endif
 
+PINCTRL_DT_INST_DEFINE(1);
+
 static const struct uart_sifive_device_config uart_sifive_dev_cfg_1 = {
 	.port         = DT_INST_REG_ADDR(1),
 	.sys_clk_freq = DT_INST_PROP(1, clock_frequency),
 	.baud_rate    = DT_INST_PROP(1, current_speed),
 	.rxcnt_irq    = CONFIG_UART_SIFIVE_PORT_1_RXCNT_IRQ,
 	.txcnt_irq    = CONFIG_UART_SIFIVE_PORT_1_TXCNT_IRQ,
+	.pcfg	      = PINCTRL_DT_INST_DEV_CONFIG_GET(1),
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	.cfg_func     = uart_sifive_irq_cfg_func_1,
 #endif