Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Support Chisel6 for RTL-sim/VLSI/FPGA flows #1854

Merged
merged 17 commits into from
May 13, 2024
Merged

Support Chisel6 for RTL-sim/VLSI/FPGA flows #1854

Changes from 1 commit
Commits
Show all changes
17 commits
Select commit Hold shift + click to select a range
838cd9a
Remove hwacha/esp-tools
jerryz123 Apr 19, 2024
c8c176b
Remove sha3 due to no chisel6 compatibility
jerryz123 Apr 19, 2024
83c56ec
Bump mempress to modern chisel
jerryz123 May 13, 2024
58dc407
Rename dsptools/fixedpoint submods to chisel3
jerryz123 Apr 20, 2024
b37e550
Add chisel6 fixedpoint/dsptools
jerryz123 Apr 20, 2024
718f197
Add standalone midas-targetutils
jerryz123 Apr 20, 2024
0d51cc3
Bump chisel6-dsptools
jerryz123 Apr 22, 2024
c2d4180
Move chipyard stage to separate directory
jerryz123 Apr 22, 2024
4b28789
Add chisel6 stage
jerryz123 Apr 23, 2024
2be92bc
Update chisel6 chipyard-stage API
jerryz123 Apr 23, 2024
ab077ef
Add stage/stage-chisel3 to makefile source-finder
jerryz123 Apr 23, 2024
295435a
Bump fpga-shells to fix chisel6-breaking API
jerryz123 Apr 23, 2024
daf4b64
Update fpga-flow to remove chisel6-incompatible APIs
jerryz123 Apr 23, 2024
39092e9
Switch RTL-sim/FPGA/VLSI flows to chisel6
jerryz123 Apr 23, 2024
ab78bbe
Precisely define firesim source directories
jerryz123 May 12, 2024
743681b
Dedup apache dependencies in build.sbt
jerryz123 May 12, 2024
3cda03a
Combine chipyard-full-flow into one job
jerryz123 Apr 23, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Prev Previous commit
Next Next commit
Add stage/stage-chisel3 to makefile source-finder
  • Loading branch information
@jerryz123
jerryz123 committed May 13, 2024
commit ab077ef494b59bd6957911f2e725c1f05a4daaf8
2 changes: 1 addition & 1 deletion common.mk
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ CHECK_SUBMODULES_COMMAND = echo "Checking all submodules in generators/ are init

SCALA_EXT = scala
VLOG_EXT = sv v
CHIPYARD_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim fpga/fpga-shells fpga/src)
CHIPYARD_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim fpga/fpga-shells fpga/src tools/stage tools/stage-chisel3)
CHIPYARD_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(SCALA_EXT))
CHIPYARD_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(VLOG_EXT))
TAPEOUT_SOURCE_DIRS = $(addprefix $(base_dir)/,tools/tapeout)
Expand Down