processor-design

Codex skills for Chisel/RISC-V processor development: microarchitecture, RTL verification, Vivado timing analysis, and FPGA optimization.

RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

18-bit processor implementation using Logisim

Custom processor implemented in logisim-evolution

Semester Project for CSC4210 Computer Architecture, a 4 task processor design.

Superscalar CPU simulation models how modern processors execute instructions in parallel and manage hazards, analyzing and scheduling Python function instructions using advanced CPU features.