SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU
Implementation of Booth's algorithm for signed binary multiplication. It includes code designed for the PDUA processor, developed by the Pontificia Universidad Javeriana. The algorithm is provided in assembly language and includes its translation into executable binary instructions.
Microcontroller implementation (VHDL) using an expanded version of the R8 ISA (PUCRS - Porto Alegre, Brasil), aiming FPGA synthesis
A hardware-software co-design of a Mini-Transformer next-token predictor, featuring a Single-Layer Self-Attention pipeline implemented in pure RISC-V assembly and a custom 16-bit processor datapath designed in Logisim with a dedicated ISA optimized for parallel vector dot products and accumulations.
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