maze1377 / pipeline-mips-verilog Star 53 Code Issues Pull requests A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall mips verilog mips-architecture mips32 pipline control-hazards mips-instruction data-hazards pipeline-mips-verilog Updated Jan 28, 2025 Verilog
Ali-975 / rv32i-5-stage-pipelined-processor Star 0 Code Issues Pull requests RISC-V RV32I 5-stage pipelined processor implemented in SystemVerilog with RTL design, testbench, and hex-based instruction memory. data-flow riscv stages control-hazards data-hazards 5-stage-pipelined-processor rv32i-processor Updated Sep 13, 2025 SystemVerilog
sebastian-wardzinski / computer-architecture Star 0 Code Issues Pull requests ECE552: Computer Architecture — Fall 2020. multithreading computer-architecture branch-prediction cache-coherence cache-optimization instruction-level-parallelism memory-consistency dynamic-scheduling control-hazards data-hazards multiprocessor-systems superscalar-cpu Updated Dec 28, 2021 C
